EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
Bit 5 (PWM1E): PWM1 enable bit
0 = PWM1 is off (default value), and its related pin carries out the P51
function;
1 = PWM1 is on, and its related pin is automatically set to output.
Bit 4:
Unimplemented, read as ‘0’
Bit 3 (T1EN):
TMR1 enable bit
0 = TMR1 is off (default value)
1 = TMR1 is on
Bit 2 ~ Bit 0 (T1P2 ~ T1P0): TMR1 clock prescale option bits
T1P2
T1P1
T1P0
Prescale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2 (default)
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.5 IOC90 (TMRCON: TIMER Control Register)
7
6
5
4
3
2
1
0
T3EN
T2EN
T3P2
T3P1
T3P0
T2P2
T2P1
T2P0
Bit 7 (T3EN): TMR3 enable bit
0 = TMR3 is off (default value)
1 = TMR3 is on
Bit 6 (T2EN): TMR2 enable bit
0 = TMR2 is off (default value)
1 = TMR2 is on
Bit 5 ~ Bit 3 (T3P2 ~ T3P0): TMR3 clock prescale option bits
T3P2
T3P1
T3P0
Prescale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2(default)
1:4
1:8
1:16
1:32
1:64
1:128
1:256
20 •
Product Specification (V1.0) 06.23.2005
(This specification is subject to change without further notice)