EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
Bit 3 (/PH3): Control bit is used to enable the pull-high of the P53 pin.
Bit 2 (/PH2): Control bit is used to enable the pull-high of the P52 pin.
Bit 1 (/PH1): Control bit is used to enable the pull-high of the P51 pin.
Bit 0 (/PH0): Control bit is used to enable the pull-high of the P50 pin.
6.2.10 IOCE0 (WDT Control Register)
7
6
5
4
3
2
1
0
WDTE
EIS
PSWE
PSW2
PSW1
PSW0
“0”
“0”
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer
0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable
Bit 6 (EIS):
Control bit is used to define the function of the P50 (/INT) pin
0 = P50, normal I/O pin
1 = /INT, external interrupt pin. In this case, the I/O control bit of P50
(Bit 0 of IOC50) must be set to "1"
NOTE
■ When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin
can also be read by way of reading Port 5 (R5). Refer to Fig. 6-4 (I/O Port and I/O
Control Register Circuit for P50(/INT)) under Section 6.4 (I/O Ports).
■ EIS is both readable and writable.
Bit 5 (PSWE): Prescaler enable bit for WDT
0 = prescaler disable bit. WDT rate is 1:1
1 = prescaler enable bit. WDT rate is set as Bit4~Bit2
Bit 4 ~ Bit 2 (PSW2 ~ PSW0): WDT prescaler bits.
PSW2 PSW1 PSW0
WDT Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 1 ~ Bit 0: Unimplemented, read as ‘0’
Product Specification (V1.0) 06.23.2005
• 23
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
