EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
Bit 0 (TCIE):
TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
6.2.12 IOC51 (PRD1: PWM1 Time Period)
The content of IOC51 is the time period (time base) of PWM1. The frequency of PWM1
is the reverse of the period.
6.2.13 IOC61 (PRD2: PWM2 Time Period)
The content of IOC61 is the time period (time base) of PWM2. The frequency of PWM2
is the reverse of the period.
6.2.14 IOC71 (PRD3: PWM3 Time Period)
The content of IOC71 is the time period (time base) of PWM3. The frequency of PWM3
is the reverse of the period.
6.2.15 IOC81 (DT1L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM1 Duty Cycle)
A specified value keeps the output of PWM1 to stay high until the value matches with
TMR1.
6.2.16 IOC91 (DT2L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM2 Duty Cycle)
A specified value keeps the output of PWM2 to stay high until the value matches with
TMR2.
6.2.17 IOCA1 (DT3L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM3 Duty Cycle)
A specified value keeps the output of PWM3 to stay high until the value matches with
TMR3.
6.2.18 IOCB1 (DTH: the Most Significant Bits of PWM Duty Cycle)
7
6
5
4
3
2
1
0
“0”
“0”
PWM3[9] PWM3[8] PWM2[9] PWM2[8] PWM1[9] PWM1[8]
Bit 7 & Bit 6:
Unimplemented, read as ‘0’.
Bit 5 & Bit 4 (PWM3[9], PWM3[8]): The Most Significant Bits of PWM3 Duty Cycle.
Bit 3 & Bit 2 (PWM2[9], PWM2[8]): The Most Significant Bits of PWM2 Duty Cycle.
Bit 1 & Bit 0 (PWM1[9], PWM1[8]): The Most Significant Bits of PWM1 Duty Cycle.
Product Specification (V1.0) 06.23.2005
• 25
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
