EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
NOTE
Note the pin priority of the COS1 and COS0 bits of IOCA0 Control register when
P60/ADE0 acts as analog input or as digital I/O. The Comparator/OP select bits are as
shown in a table under Section 6.2.6, IOCA0 (CMPCON: Comparator Control Register).
The P60/ADE0/CO pin priority is as follows:
P60/ADE0/CO PRIORITY
High
CO
Medium
ADE0
Low
P60
6.1.8 R9 (ADCON: ADC Control Register)
7
6
5
4
3
2
1
0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Bit 7 (VREFS): The input source of the Vref of the ADC
0 = The Vref of the ADC is connected to Vdd (default value), and the
P53/VREF pin carries out the function of P53
1 = The Vref of the ADC is connected to P53/VREF
NOTE
The P53/PWM3/VREF pin cannot be applied to PWM3 and VREF at the same time. If
P53/PWM3/VREF acts as VREF analog input pin, then PWM3E must be “0”..
The P53/PWM3/VREF pin priority is as follows:
P53/PWM3/VREF PIN PRIORITY
High
Medium
PWM3
Low
P53
VREF
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of oscillator clock rate of ADC
00 = 1: 4 (default value)
01 = 1: 16
10 = 1: 64
11 = 1: WDT ring oscillator frequency
CKR0:CKR1
Operation Mode
Fsco/4
Max. Operation Frequency
00
01
10
11
1 MHz
4 MHz
16MHz
-
Fsco/16
Fsco/64
Internal RC
Product Specification (V1.0) 06.23.2005
• 13
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
