EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
6.1.4 R3 (Status Register)
7
6
5
4
3
2
1
0
IOCS
PS1
PS0
T
P
Z
DC
C
Bit 7 (IOCS): Select the Segment of IO control register.
0 = Segment 0 (IOC50 ~ IOCF0) selected
1 = Segment 1 (IOC51 ~ IOCF1) selected
Bit 6 ~ Bit 5 (PS1 ~ PS0): Page select bits. PS0 ~ PS1 are used to select a program
memory page. When executing a "JMP," "CALL," or other instructions
which cause the program counter to change (e.g., MOV R2, A), PS0 ~
PS1 are loaded into the 11th and 12th bits of the program counter where
it selects one of the available program memory pages. Note that RET
(RETL, RETI) instruction does not change the PS0~PS1 bits. That is,
the return will always be back to the page from where the subroutine was
called, regardless of the current PS0 ~ PS1 bits setting.
PS1
PS0
Program Memory Page [Address]
Page 0 [000-3FF]
0
0
1
1
0
1
0
1
Page 1 [400-7FF]
Page 2 [800-BFF]
Page 3 [C00-FFF]
Bit 4 (T):
Bit 3 (P):
Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands, or during
power on and reset to 0 by WDT time-out.
Power-down bit. Set to 1 during power-on or by a "WDTC" command
and reset to 0 by a "SLEP" command.
NOTE
Bit 4 & Bit 3 (T & P) are read only.
Bit 2 (Z):
Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7 & Bit 6: are used to select Banks 0 ~ 3.
Bit 5 ~ Bit 0: are used to select registers (address: 00 ~ 3F) in the indirect address
mode.
See the table under Section 6.1.3.1 Data Memory Configuration for the configuration of
the data memory.
Product Specification (V1.0) 06.23.2005
• 11
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
