EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
6.1.3.1 Data Memory Configuration
PAGE Registers IOC PAGE Registers
Address
IOC PAGE Registers
R0 (Indirect Addressing
00
Reserve
Reserve
Register)
01
02
R1 (Time Clock Counter)
R2 (Program Counter)
Reserve
Reserve
Reserve
Reserve
03
04
R3 (Status Register)
Reserve
Reserve
Reserve
Reserve
R4 (RAM Select Register)
IOC50 (I/O Port Control
IOC51 (PRD1: PWM1 time
05
06
07
08
09
0A
0B
0C
0D
R5 (Port5)
R6 (Port6)
R7 (Port7)
Register)
period)
IOC60 (I/O Port Control
IOC61 (PRD2: PWM2 time
Register)
period)
IOC70 (I/O Port Control
IOC71 (PRD3: PWM3 time
Register)
period)
IOC81 (DT1L:Duty cycle of
R8 (ADC Input Select Register) IOC80 (PWM Control Register)
PWM1)
IOC91 (DT2L: Duty cycle of
R9 (ADC Control Register)
IOC90 (TIMER Control Register)
PWM2)
IOCA0
RA (ADC Offset Calibration
IOCA1 (DT3L: Duty cycle of
Register)
PWM3)
(Comparator Control Register)
RB (ADDATA: ADC data
IOCB0
IOCB1 (DTH: Duty cycle of
PWM)
bit11~bit4)
(Pull-down Control Register)
IOCC0
RC (ADDATA1H: ADC data
IOCC1 (TIMER1L: PWM1 timer)
IOCD1 (TIMER2L: PWM2 timer)
bit11~bit8)
(Open-drain Control Register)
IOCD0
RD (ADDATA1L: ADC data
bit7~bit0)
(Pull-high Control Register)
0E
0F
RE (Wake-up Control Register) IOCE0 (WDT Control Register) IOCE1 (TIMER3L: PWM3 timer)
RF (Interrupt Status Register)
IOCF0 (Interrupt Mask Register) IOCF1 (TMRH: PWM timer)
10
1F
General Registers
20
3F
Bank 0 Bank 1 Bank 2 Bank 3
10 •
Product Specification (V1.0) 06.23.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
