EM78P350N
8-Bit Microprocessor with OTP ROM
SCK/P80 (Pin 6):
Serial Clock
Generated by a master device
Synchronize the data communication on both the SDI and SDO pins.
The CES (located in Register 0x0D) is used to select the edge to communicate.
The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
communication.
The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode
Timing is shown in Fig.6-12 and 6-13.
/SS/P75 (Pin 4):
Slave Select; negative logic
Generated by a master device to signify the slave to receive data
Goes low before the first cycle of SCK appears, and remains low until the last
(eighth) cycle is completed,
Ignores the data on the SDI and SDO pins while /SS is high, since the SDO is no
longer driven.
Timing is shown in Fig.6-12 and 6-13.
6.5.4 Programming the Related Registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2
and Table 3.
Table 1 Related Control Registers of the SPI Mode
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0D
NA
*SPIC/RD
CES
SPIE
SRO
SSE
SOUTC
“0”
SBR2
SBR1
SBR0
SPIIE SPIF
TM4IF
TM4E TM4P1 TM4P0
T4CR/IOC9
−
SPIC: SPI Control Register.
Bit 7 (CES): Clock Edge Select bit
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on
hold during the low level.
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on
hold during the high level.
Bit 6 (SPIE): SPI Enable bit
0 = Disable SPI mode
1 = Enable SPI mode
42 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
