EM78P350N
8-Bit Microprocessor with OTP ROM
Bit 3: Unimplemented, read as ‘0’
Bit 2 (TM4E): Timer 4 Function Enable bit
0 : Disable Timer 4 function (default)
1 : Enable Timer 4 function
Bit 1~Bit 0 (TM4P): Timer 4 Prescaler bit
TM4P1
TM4P0
Prescaler Rate
0
0
1
1
0
1
0
1
1:1
1:4
1:8
1:16
Table 2 Related Status/Data Registers of the SPI Mode
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0X0A
0x0B
0x0C
SPIRB/RA SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
SPIWB/RB SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
SPIS/RC DORD
TD1
TD0 T4ROS OD3
OD4
-
RBF
SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to
SPIRB from SPISR. The RBF bit in the SPIS register will also be set.
SPIWB: SPI Write Buffer. As a transmitted data is loaded, the SPIS register stands by
and start to shift the data when sensing SCK edge with SSE set to “1”.
SPIS: SPI Status register
Bit 7 (DORD): Data transmission order
0 : Shift left (MSB first)
1 : Shift right (LSB first)
Bit 6 ~ Bit 5: SDO Status Output Delay Times Options. There is no action in slave mode.
TD1
TD0
Delay Time
0
0
1
1
0
1
0
1
8 CLK
16 CLK
24 CLK
32 CLK
Bit 4 (T4ROS): Timer 4 Read Out Buffer Select Bit
0 : Read Value from Timer 4 Preset Register
1 : Read Value from Timer 4 Counter Register
Bit 3 (OD3) Open-Drain Control bit (P81)
0 : Open-drain disable for Sout
1 : Open-drain enable for Sout
Bit 2 (OD4): Open Drain-Control bit (P80)
0 : Open-drain disable for SCK
1 : Open-drain enable for SCK
44 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
