EM78P350N
8-Bit Microprocessor with OTP ROM
Bit 5 (SRO): SPI Read Overflow bit
0 = No overflow occurs
1 = A new data is received while the previous data is still being on hold in
the SPIRB register. Under this condition, the data in SPIS register will
be destroyed. To avoid setting this bit, users should read the SPIRB
register even if the transmission is implemented only.
NOTE
This can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable bit
0 = Reset as soon as the shifting is completed and the next byte is ready
to shift.
1 = Start to shift, and remains on 1 while the current byte continues to
transmit.
NOTE
This bit can be reset by hardware only.
Bits 2~0 (SBRS):SPI Baud Rate Select Bits
SBRS2 (Bit 2)
SBRS1 (Bit 1)
SBRS0 (Bit 0)
Mode
Baud Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Master
Master
Master
Master
Master
Slave
Fsco/2
Fsco/4
Fsco/8
Fsco/16
Fsco/32
/SS enable
/SS disable
TMR4/2
Slave
Master
Note: In Master mode, /SS is disabled.
T4CR: Timer 4 Control Register
Bit 7(SPIIE): SPI Interrupt enable bit
0 : Disable SPI interrupt
1 : Enable SPI interrupt
Bit 6 (SPIIF): SPI interrupt flag. Set by data transmission complete, flag by software.
Bit 5 (TM4IE): TM4IE interrupt enable bit
0 : Disable TM4IE interrupt
1 : Enable TM4IE interrupt
Bit 3 (TM4IF): Timer 4 interrupt flag. Set by the comparator at Timer 4 application, flag
is cleared by software.
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
