EM78P350N
8-Bit Microprocessor with OTP ROM
SPI transmission order
After serial data output SDO status select
SDO status output delay times
SPI handshake pin
Up to 8 MHz (maximum) bit frequency,
SDO
SPIW
SPIW Reg
Reg
SPIW
SPIW Reg
Reg
SPIR Reg
SPIR Reg
/SS
SDI
SPI Module
SPIS Reg
Bit 7
SCK
Master Device
Slave Device
Fig. 6-7 SPI Master/Slave Communication
SDI
SDO
SCK
/SS
Vdd
Master
P50
P51
P52
P53
Slave Device 1
Slave Device 2
Slave Device 3
Slave Device 4
Fig. 6-8 SPI Configuration of Single-Master and Multi-Slave
38 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)