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EDE1108AFBG-8G-F 参数 Datasheet PDF下载

EDE1108AFBG-8G-F图片预览
型号: EDE1108AFBG-8G-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR2 SDRAM [1G bits DDR2 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 78 页 / 734 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDE1108AFBG  
ODT DC Electrical Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)  
Parameter  
Symbol  
Rtt1 (eff)  
Rtt2 (eff)  
Rtt3 (eff)  
VM  
min.  
60  
typ.  
75  
max.  
90  
Unit  
Note  
Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Ω  
Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Ω  
Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Ω  
Deviation of VM with respect to VDDQ/2  
1
1
1
1
120  
40  
150  
50  
180  
60  
6  
+6  
%
Note: 1. Test condition for Rtt measurements.  
Measurement Definition for Rtt (eff)  
Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.  
VIH(AC), and VDDQ values defined in SSTL_18.  
VIH(AC) VIL(AC)  
Rtt(eff ) =  
I(VIH(AC))I(VIL(AC))  
Measurement Definition for VM  
Measure voltage (VM) at test pin (midpoint) with no load.  
2×VM  
VM =  
-1 ×100  
VDDQ  
OCD Default Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)  
Parameter  
min.  
12.6  
0
typ.  
max.  
23.4  
4
Unit  
Notes  
1, 5  
Output impedance  
Pull-up and pull-down mismatch  
Output slew rate  
18  
1, 2  
1.5  
5
V/ns  
3, 4  
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;  
(VOUTVDDQ)/IOH must be less than 23.4for values of VOUT between VDDQ and VDDQ280mV.  
Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;  
VOUT/IOL must be less than 23.4for values of VOUT between 0V and 280mV.  
2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and  
voltage.  
3. Slew rate measured from VIL(AC) to VIH(AC).  
4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate  
as measured from AC to AC. This is guaranteed by design and characterization.  
5. DRAM I/O specifications for timing, voltage, and slew rate are no longer applicable if OCD is changed  
from default settings.  
Preliminary Data Sheet E1430E20 (Ver. 2.0)  
12