EDE1108AFBG
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2-800, 667]
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8E
-8G
-6E
Speed bin
Parameter
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
DDR2-667 (5-5-5)
Symbol
tRCD
tRP
min.
12.5
12.5
57.5
max.
min.
15
max.
min.
15
max.
Unit
ns
Notes
Active to read or write
command delay
Precharge command period
15
15
ns
Active to active/auto-refresh
command time
tRC
60
60
ns
DQ output access time from
CK, /CK
tAC
−400
−350
+400
+350
−400
−350
+400
+350
−450
−400
+450
+400
ps
ps
10
10
DQS output access time from
CK, /CK
tDQSCK
CK high-level width
CK low-level width
tCH (avg) 0.48
0.52
0.52
0.48
0.48
0.52
0.52
0.48
0.48
0.52
0.52
tCK (avg) 13
tCK (avg) 13
tCL(avg)
0.48
Min.
Min.
Min.
CK half period
tHP
(tCL(abs),
tCH(abs))
(tCL(abs),
tCH(abs))
(tCL(abs),
tCH(abs))
ps
ps
6, 13
Clock cycle time
(CL = 6)
tCK (avg) 2500
8000
2500
8000
3000
8000
13
(CL = 5)
tCK (avg) 2500
tCK (avg) 3750
tCK (avg) 5000
tDH (base) 125
tDS (base) 50
8000
8000
8000
3000
3750
5000
125
8000
8000
8000
3000
3750
5000
175
8000
8000
8000
ps
ps
ps
ps
ps
13
13
13
5
(CL = 4)
(CL = 3)
DQ and DM input hold time
DQ and DM input setup time
50
100
4
Control and Address input
pulse width for each input
tIPW
tDIPW
tHZ
0.6
0.6
0.6
tCK (avg)
tCK (avg)
DQ and DM input pulse width
for each input
0.35
0.35
0.35
Data-out high-impedance time
from CK,/CK
tAC max.
tAC max.
tAC max. ps
10
10
10
DQS, /DQS low-impedance
time from CK,/CK
tLZ (DQS) tAC min. tAC max. tAC min. tAC max. tAC min. tAC max. ps
DQ low-impedance time from
CK,/CK
2 ×
2 ×
2 ×
tLZ (DQ)
tAC max.
tAC max.
tAC max. ps
tAC min.
tAC min.
tAC min.
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
tQHS
tQH
200
300
200
300
240
340
ps
ps
ps
DQ hold skew factor
7
8
DQ/DQS output hold time from
DQS
tHP –
tQHS
tHP –
tQHS
tHP –
tQHS
DQS latching rising transitions
to associated clock edges
tDQSS
−0.25
+0.25
−0.25
+0.25
−0.25
+0.25
tCK (avg)
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
0.35
0.35
0.35
0.35
tCK (avg)
tCK (avg)
DQS falling edge to CK setup
time
tDSS
tDSH
0.2
0.2
0.2
0.2
0.2
0.2
tCK (avg)
tCK (avg)
DQS falling edge hold time
from CK
Mode register set command
cycle time
tMRD
2
2
2
nCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK (avg)
Preliminary Data Sheet E1430E20 (Ver. 2.0)
14
ELPIDA [ ELPIDA MEMORY ]
