EDE1108AFBG
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
5-5-5
5
DDR2-800
6-6-6
6
DDR2-667
5-5-5
5
Parameter
Unit
tCK
ns
CL (IDD)
tRCD (IDD)
tRC (IDD)
12.5
57.5
7.5
15
15
60
60
ns
tRRD (IDD)
tFAW (IDD)
tCK (IDD)
7.5
7.5
ns
35
35
37.5
3
ns
2.5
2.5
ns
tRAS (min.)(IDD)
tRAS (max.)(IDD)
tRP (IDD)
45
45
45
ns
70000
12.5
127.5
70000
15
70000
15
ns
ns
tRFC (IDD)
127.5
127.5
ns
IDD7 Timing Patterns for 8 Banks
The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables.
Speed bins
DDR2-667
DDR2-800
Timing Patterns
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Remark: A = Active. RA = Read with auto precharge. D = Deselect
Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using
a Burst length = 4.
2. Control and address bus inputs are STABLE during DESELECTs.
3. IOUT = 0mA.
Preliminary Data Sheet E1430E20 (Ver. 2.0)
10
ELPIDA [ ELPIDA MEMORY ]
