EDE1108AFBG
-8E
-8G
-6E
DDR2-667 (5-5-5)
Speed bin
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
Parameter
Symbol
tWPRE
min.
0.35
max.
min.
0.35
max.
min.
0.35
max.
Unit
Notes
Write preamble
tCK (avg)
Address and control input hold
time
tIH (base) 250
tIS (base) 175
250
175
275
200
ps
ps
5
4
Address and control input
setup time
Read preamble
Read postamble
tRPRE
tRPST
0.9
1.1
0.9
1.1
0.9
1.1
tCK (avg) 11
0.4
0.6
0.4
0.6
0.4
0.6
tCK (avg) 12
Active to precharge command tRAS
Active to auto-precharge delay tRAP
45
70000
45
70000
45
70000
ns
ns
tRCD min.
tRCD min.
tRCD min.
Active bank A to active bank B
tRRD
7.5
7.5
7.5
ns
command period
Four active window period
tFAW
35
2
35
2
37.5
2
ns
/CAS to /CAS command delay tCCD
nCK
ns
Write recovery time
tWR
15
15
15
WR +
RU (tRP/
tCK (avg))
WR +
RU (tRP/
tCK (avg))
WR +
RU (tRP/
tCK (avg))
Auto precharge write recovery
+ precharge time
tDAL
nCK
1, 9
Internal write to read command
delay
tWTR
tRTP
7.5
7.5
7.5
ns
14
Internal read to precharge
command delay
7.5
7.5
7.5
ns
Exit self-refresh to a non-read
command
tXSNR
tXSRD
tXP
tRFC + 10
tRFC + 10
tRFC + 10
ns
Exit self-refresh to a read
command
200
2
200
2
200
2
nCK
nCK
nCK
Exit precharge power down to
any non-read command
Exit active power down to read
command
tXARD
2
2
2
3
Exit active power down to read
command
tXARDS
8 − AL
8 − AL
7 − AL
nCK
2, 3
(slow exit/low power mode)
CKE minimum pulse width
(high and low pulse width)
tCKE
tOIT
3
3
3
nCK
ns
Output impedance test driver
delay
0
12
12
0
12
12
0
12
12
MRS command to ODT update
delay
tMOD
tRFC
0
0
0
ns
Auto-refresh to active/auto-
refresh command time
127.5
127.5
127.5
ns
Average periodic refresh
interval
(0°C ≤ TC ≤ +85°C)
tREFI
tREFI
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
ns
(+85°C < TC ≤ +95°C)
Minimum time clocks remains
ON after CKE asynchronously tDELAY
drops low
tIS +
tCK(avg) +
tIH
tIS +
tCK(avg) +
tIH
tIS +
tCK(avg) +
tIH
Preliminary Data Sheet E1430E20 (Ver. 2.0)
15
ELPIDA [ ELPIDA MEMORY ]
