EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
13.6.3 Synchronous Characteristics
Parameter
Symbol
tCK
-7A
-75
1A
Unit
ns
Note
MIN.
7.5
MAX.
12
MIN.
7.5
MAX.
12
MIN.
10
MAX.
12
Clock cycle time
CL = 2.5
CL = 2
7.5
12
10
12
10
12
CLK high-level width
CLK low-level width
tCH
tCL
0.45
0.45
–0.75
–0.75
0.55
0.55
0.75
0.75
0.5
0.45
0.45
–0.75
–0.75
0.55
0.55
0.75
0.75
0.5
0.45
0.45
–0.8
–0.8
0.55
0.55
0.8
tCK
tCK
ns
ns
ns
DQ output access time from CLK, /CLK
DQS output access time from CLK, /CLK
tAC
tDQSCK
tDQSQ
0.8
DQS-DQ skew (for DQS and associated
0.6
DQ signals)
DQS-DQ skew (for DQS and all DQ
tDQSQA
tLZ
0.5
0.5
0.6
0.8
0.8
ns
ns
ns
ns
signals)
Data out low-impedance time from CLK,
–0.75
–0.75
MIN.
0.75
0.75
–0.75
–0.75
MIN.
0.75
0.75
–0.8
–0.8
MIN.
/CLK
Data out high-impedance time from CLK,
tHZ
/CLK
Half clock period
tHP
(tCH, tCL)
0.9
(tCH, tCL)
0.9
(tCH, tCL)
0.9
Read preamble
tRPRE
tRPST
tQH
1.1
0.6
1.1
0.6
1.1
0.6
tCK
tCK
ns
Read postamble
0.4
0.4
0.4
DQ output hold time from DQS
tHP –
0.75
0.5
tHP –
0.75
0.5
tHP – 1
DQ and DM input setup time
DQ and DM input hold time
tDS
tDH
0.6
0.6
2
ns
ns
ns
0.5
0.5
DQ and DM input pulse width (for each
input)
tDIPW
1.75
1.75
Write preamble setup time
tWPRES
tWPRE
tWPST
tDQSS
0
0
0
ns
tCK
tCK
tCK
Write preamble
Write postamble
0.25
0.4
0.25
0.4
0.25
0.4
0.6
0.6
0.6
Write command to first DQS latching
transition
0.75
1.25
0.75
1.25
0.75
1.25
DQS input high pulse width
tDQSH
tDQSL
tDSS
tDSH
tIS
0.35
0.35
0.2
0.2
0.9
0.9
2.2
1
0.35
0.35
0.2
0.2
0.9
0.9
2.2
1
0.35
0.35
0.2
0.2
1.1
1.1
2.5
1
tCK
tCK
tCK
tCK
ns
ns
ns
tCK
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Internal write to read command delay
tIH
tIPW
tWTR
41
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
