DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 113: UART2_USR_REG (0x5000117C)
Bit
Mode Symbol
Description
Reset
1
R
UART_TFNF
Transmit FIFO Not Full.
0x1
This is used to indicate that the transmit FIFO in not full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
This bit is cleared when the TX FIFO is full.
0
-
-
Reserved
0x0
Table 114: UART2_TFL_REG (0x50001180)
Bit
Mode Symbol
UART_TRANSMIT_F
IFO_LEVEL
Description
Reset
15:0
R
Transmit FIFO Level.
This is indicates the number of data entries in the transmit
FIFO.
0x0
Table 115: UART2_RFL_REG (0x50001184)
Bit
Mode Symbol
UART_RECEIVE_FI
FO_LEVEL
Description
Reset
15:0
R
Receive FIFO Level.
This is indicates the number of data entries in the receive
FIFO.
0x0
Table 116: UART2_SRR_REG (0x50001188)
Bit
15:3
2
Mode Symbol
Description
Reset
0x0
-
-
Reserved
W
UART_XFR
XMIT FIFO Reset.
0x0
This is a shadow register for the XMIT FIFO Reset bit
(FCR[2]). This can be used to remove the burden on soft-
ware having to store previously written FCR values (which
are pretty static) just to reset the transmit FIFO. This resets
the control portion of the transmit FIFO and treats the FIFO
as empty. Note that this bit is 'self-clearing'. It is not neces-
sary to clear this bit.
1
W
UART_RFR
RCVR FIFO Reset.
0x0
This is a shadow register for the RCVR FIFO Reset bit
(FCR[1]). This can be used to remove the burden on soft-
ware having to store previously written FCR values (which
are pretty static) just to reset the receive FIFO This resets
the control portion of the receive FIFO and treats the FIFO
as empty.
Note that this bit is 'self-clearing'. It is not necessary to clear
this bit.
0
W
UART_UR
UART Reset. This asynchronously resets the UART Ctrl and
synchronously removes the reset assertion. For a two clock
implementation both pclk and sclk domains are reset.
0x0
Table 117: UART2_SRTS_REG (0x5000118C)
Bit
Mode Symbol
Description
Reset
15:1
-
-
Reserved
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
92 of 155
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