DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 112: UART2_SRBR_STHR15_REG (0x5000116C)
Bit
Mode Symbol
R/W SRBR_STHRX
Description
Reset
7:0
Shadow Receive Buffer Register x: This is a shadow register
for the RBR and has been allocated sixteen 32-bit locations
so as to accommodate burst accesses from the master. This
register contains the data byte received on the serial input
port (sin) in UART mode or the serial infrared input (sir_in) in
infrared mode. The data in this register is valid only if the
Data Ready (DR) bit in the Line status Register (LSR) is set.
If FIFOs are disabled (FCR[0] set to zero), the data in the
RBR must be read before the next data arrives, otherwise it
will be overwritten, resulting in an overrun error. If FIFOs are
enabled (FCR[0] set to one), this register accesses the head
of the receive FIFO. If the receive FIFO is full and this regis-
ter is not read before the next data character arrives, then
the data already in the FIFO will be preserved but any
incoming data will be lost. An overrun error will also occur.
Shadow Transmit Holding Register 0: This is a shadow reg-
ister for the THR and has been allocated sixteen 32-bit loca-
tions so as to accommodate burst accesses from the master.
This register contains data to be transmitted on the serial
output port (sout) in UART mode or the serial infrared output
(sir_out_n) in infrared mode. Data should only be written to
the THR when the THR Empty (THRE) bit (LSR[5]) is set. If
FIFO's are disabled (FCR[0] set to zero) and THRE is set,
writing a single character to the THR clears the THRE. Any
additional writes to the THR before the THRE is set again
causes the THR data to be overwritten. If FIFO's are enabled
(FCR[0] set to one) and THRE is set, x number of characters
of data may be written to the THR before the FIFO is full.
The number x (default=16) is determined by the value of
FIFO Depth that you set during configuration. Any attempt to
write data when the FIFO is full results in the write data being
lost.
0x0
Table 113: UART2_USR_REG (0x5000117C)
Bit
15:5
4
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
UART_RFF
Receive FIFO Full.
0x0
This is used to indicate that the receive FIFO is completely
full.
0 = Receive FIFO not full
1 = Receive FIFO Full
This bit is cleared when the RX FIFO is no longer full.
3
2
R
R
UART_RFNE
UART_TFE
Receive FIFO Not Empty.
This is used to indicate that the receive FIFO contains one or
more entries.
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
0x0
0x1
This bit is cleared when the RX FIFO is empty.
Transmit FIFO Empty.
This is used to indicate that the transmit FIFO is completely
empty.
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
This bit is cleared when the TX FIFO is no longer empty.
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
91 of 155
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