DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 156: I2C_ENABLE_REG (0x5000136C)
Bit
Mode Symbol
R/W CTRL_ENABLE
Description
Reset
0
Controls whether the controller is enabled.
0: Disables the controller (TX and RX FIFOs are held in an
erased state)
0x0
1: Enables the controller
Software can disable the controller while it is active. How-
ever, it is important that care be taken to ensure that the con-
troller is disabled properly. When the controller is disabled,
the following occurs:
* The TX FIFO and RX FIFO get flushed.
* Status bits in the IC_INTR_STAT register are still active
until the controller goes into IDLE state.
If the module is transmitting, it stops as well as deletes the
contents of the transmit buffer after the current transfer is
complete. If the module is receiving, the controller stops the
current transfer at the end of the current byte and does not
acknowledge the transfer.
There is a two ic_clk delay when enabling or disabling the
controller
Table 157: I2C_STATUS_REG (0x50001370)
Bit
15:7
6
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
SLV_ACTIVITY
Slave FSM Activity Status. When the Slave Finite State
Machine (FSM) is not in the IDLE state, this bit is set.
0: Slave FSM is in IDLE state so the Slave part of the con-
troller is not Active
0x0
1: Slave FSM is not in IDLE state so the Slave part of the
controller is Active
5
R
MST_ACTIVITY
Master FSM Activity Status. When the Master Finite State
Machine (FSM) is not in the IDLE state, this bit is set.
0: Master FSM is in IDLE state so the Master part of the con-
troller is not Active
0x0
1: Master FSM is not in IDLE state so the Master part of the
controller is Active
4
3
2
R
R
R
RFF
Receive FIFO Completely Full. When the receive FIFO is
completely full, this bit is set. When the receive FIFO con-
tains one or more empty location, this bit is cleared.
0: Receive FIFO is not full
0x0
0x0
0x1
1: Receive FIFO is full
RFNE
TFE
Receive FIFO Not Empty. This bit is set when the receive
FIFO contains one or more entries; it is cleared when the
receive FIFO is empty.
0: Receive FIFO is empty
1: Receive FIFO is not empty
Transmit FIFO Completely Empty. When the transmit FIFO is
completely empty, this bit is set. When it contains one or
more valid entries, this bit is cleared. This bit field does not
request an interrupt.
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
1
R
TFNF
Transmit FIFO Not Full. Set when the transmit FIFO contains
one or more empty locations, and is cleared when the FIFO
is full.
0x1
0: Transmit FIFO is full
1: Transmit FIFO is not full
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
107 of 155
© 2014 Dialog Semiconductor
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