DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 145: I2C_CLR_INTR_REG (0x50001340)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
CLR_INTR
Read this register to clear the combined interrupt, all individ- 0x0
ual interrupts, and the I2C_TX_ABRT_SOURCE register.
This bit does not clear hardware clearable interrupts but soft-
ware clearable interrupts. Refer to Bit 9 of the
I2C_TX_ABRT_SOURCE register for an exception to clear-
ing I2C_TX_ABRT_SOURCE
Table 146: I2C_CLR_RX_UNDER_REG (0x50001344)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
CLR_RX_UNDER
Read this register to clear the RX_UNDER interrupt (bit 0) of
0x0
the
I2C_RAW_INTR_STAT register.
Table 147: I2C_CLR_RX_OVER_REG (0x50001348)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
CLR_RX_OVER
Read this register to clear the RX_OVER interrupt (bit 1) of
0x0
the
I2C_RAW_INTR_STAT register.
Table 148: I2C_CLR_TX_OVER_REG (0x5000134C)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
CLR_TX_OVER
Read this register to clear the TX_OVER interrupt (bit 3) of
the I2C_RAW_INTR_STAT register.
0x0
Table 149: I2C_CLR_RD_REQ_REG (0x50001350)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
CLR_RD_REQ
Read this register to clear the RD_REQ interrupt (bit 5) of
the I2C_RAW_INTR_STAT register.
0x0
Table 150: I2C_CLR_TX_ABRT_REG (0x50001354)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
CLR_TX_ABRT
Read this register to clear the TX_ABRT interrupt (bit 6) of
the
0x0
IC_RAW_INTR_STAT register, and the
I2C_TX_ABRT_SOURCE register. This also releases the TX
FIFO from the flushed/reset state, allowing more writes to
the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE
register for an exception to clearing
IC_TX_ABRT_SOURCE.
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
105 of 155
© 2014 Dialog Semiconductor
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