DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 163: I2C_ACK_GENERAL_CALL_REG (0x50001398)
Bit
15:1
0
Mode Symbol
Description
Reset
-
-
Reserved
0x0
0x0
R/W
ACK_GEN_CALL
ACK General Call. When set to 1, I2C Ctrl responds with a
ACK (by asserting ic_data_oe) when it receives a General
Call. When set to 0, the controller does not generate General
Call interrupts.
Table 164: I2C_ENABLE_STATUS_REG (0x5000139C)
Bit
15:3
2
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
SLV_RX_DATA_LOS
T
Slave Received Data Lost. This bit indicates if a Slave-
Receiver
0x0
operation has been aborted with at least one data byte
received from an I2C transfer due to the setting of
IC_ENABLE from 1 to 0. When read as 1, the controller is
deemed to have been actively engaged in an aborted I2C
transfer (with matching address) and the data phase of the
I2C transfer has been entered, even though a data byte has
been responded with a NACK. NOTE: If the remote I2C mas-
ter terminates the transfer with a STOP condition before the
controller has a chance to NACK a transfer, and IC_ENABLE
has been set to 0, then this bit is also set to 1.
When read as 0, the controller is deemed to have been dis-
abled without being actively involved in the data phase of a
Slave-Receiver transfer.
NOTE: The CPU can safely read this bit when IC_EN (bit 0)
is read as 0.
1
R
SLV_DISABLED_WH Slave Disabled While Busy (Transmit, Receive). This bit indi- 0x0
ILE_BUSY
cates if a potential or active Slave operation has been
aborted due to the setting of the IC_ENABLE register from 1
to 0. This bit is set when the CPU writes a 0 to the
IC_ENABLE register while:
(a) I2C Ctrl is receiving the address byte of the Slave-Trans-
mitter operation from a remote master; OR,
(b) address and data bytes of the Slave-Receiver operation
from a remote master. When read as 1, the controller is
deemed to have forced a NACK during any part of an I2C
transfer, irrespective of whether the I2C address matches
the slave address set in I2C Ctrl (IC_SAR register) OR if the
transfer is completed before IC_ENABLE is set to 0 but has
not taken effect.
NOTE: If the remote I2C master terminates the transfer with
a STOP condition before the the controller has a chance to
NACK a transfer, and IC_ENABLE has been set to 0, then
this bit will also be set to 1.
When read as 0, the controller is deemed to have been dis-
abled when there is master activity, or when the I2C bus is
idle.
NOTE: The CPU can safely read this bit when IC_EN (bit 0)
is read as 0.
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
110 of 155
© 2014 Dialog Semiconductor
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