DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 142: I2C_RAW_INTR_STAT_REG (0x50001334)
Bit
Mode Symbol
Description
Reset
3
R
TX_OVER
Set during transmit if the transmit buffer is filled to 32 and the
processor attempts to issue another I2C command by writing
to the IC_DATA_CMD register. When the module is disabled,
this bit keeps its level until the master or slave state
machines go into idle, and when ic_en goes to 0, this inter-
rupt is cleared
0x0
2
R
RX_FULL
Set when the receive buffer reaches or goes above the
RX_TL threshold in the I2C_RX_TL register. It is automati-
cally cleared by hardware when buffer level goes below the
threshold. If the module is disabled (I2C_ENABLE[0]=0), the
RX FIFO is flushed and held in reset; therefore the RX FIFO
is not full. So this bit is cleared once the I2C_ENABLE bit 0 is
programmed with a 0, regardless of the activity that contin-
ues.
0x0
1
0
R
R
RX_OVER
Set if the receive buffer is completely filled to 32 and an addi- 0x0
tional byte is received from an external I2C device. The con-
troller acknowledges this, but any data bytes received after
the FIFO is full are lost. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until the master
or slave state machines go into idle, and when ic_en goes to
0, this interrupt is cleared.
RX_UNDER
Set if the processor attempts to read the receive buffer when
it is empty by reading from the IC_DATA_CMD register. If the
module is disabled (I2C_ENABLE[0]=0), this bit keeps its
level until the master or slave state machines go into idle,
and when ic_en goes to 0, this interrupt is cleared.
0x0
Table 143: I2C_RX_TL_REG (0x50001338)
Bit
Mode Symbol
Description
Reset
0x0
15:5
4:0
-
-
Reserved
R/W
RX_TL
Receive FIFO Threshold Level Controls the level of entries
(or above) that triggers the RX_FULL interrupt (bit 2 in
I2C_RAW_INTR_STAT register). The valid range is 0-31,
with the additional restriction that hardware does not allow
this value to be set to a value larger than the depth of the
buffer. If an attempt is made to do that, the actual value set
will be the maximum depth of the buffer. A value of 0 sets the
threshold for 1 entry, and a value of 31 sets the threshold for
32 entries.
0x0
Table 144: I2C_TX_TL_REG (0x5000133C)
Bit
Mode Symbol
Description
Reset
0x0
15:5
4:0
-
-
Reserved
R/W
RX_TL
Transmit FIFO Threshold Level Controls the level of entries
(or below) that trigger the TX_EMPTY interrupt (bit 4 in
I2C_RAW_INTR_STAT register). The valid range is 0-31,
with the additional restriction that it may not be set to value
larger than the depth of the buffer. If an attempt is made to
do that, the actual value set will be the maximum depth of
the buffer. A value of 0 sets the threshold for 0 entries, and a
value of 31 sets the threshold for 32 entries..
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
104 of 155
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