DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 142: I2C_RAW_INTR_STAT_REG (0x50001334)
Bit
Mode Symbol
Description
Reset
15:12
11
-
-
Reserved
0x0
0x0
R
GEN_CALL
Set only when a General Call address is received and it is
acknowledged. It stays set until it is cleared either by dis-
abling controller or when the CPU reads bit 0 of the
I2C_CLR_GEN_CALL register. I2C Ctrl stores the received
data in the Rx buffer.
10
9
R
R
R
START_DET
STOP_DET
ACTIVITY
Indicates whether a START or RESTART condition has
occurred on the I2C interface regardless of whether control-
ler is operating in slave or master mode.
0x0
0x0
0x0
Indicates whether a STOP condition has occurred on the I2C
interface regardless of whether controller is operating in
slave or master mode.
8
This bit captures I2C Ctrl activity and stays set until it is
cleared. There are four ways to clear it:
=> Disabling the I2C Ctrl
=> Reading the IC_CLR_ACTIVITY register
=> Reading the IC_CLR_INTR register
=> System reset
Once this bit is set, it stays set unless one of the four meth-
ods is used to clear it. Even if the controller module is idle,
this bit remains set until cleared, indicating that there was
activity on the bus.
7
6
R
R
RX_DONE
TX_ABRT
When the controller is acting as a slave-transmitter, this bit is
set to 1 if the master does not acknowledge a transmitted
byte. This occurs on the last byte of the transmission, indi-
cating that the transmission is done.
0x0
0x0
This bit indicates if the controller, as an I2C transmitter, is
unable to complete the intended actions on the contents of
the transmit FIFO. This situation can occur both as an I2C
master or an I2C slave, and is referred to as a "transmit
abort".
When this bit is set to 1, the I2C_TX_ABRT_SOURCE regis-
ter indicates the reason why the transmit abort takes places.
NOTE: The controller flushes/resets/empties the TX FIFO
whenever this bit is set. The TX FIFO remains in this flushed
state until the register I2C_CLR_TX_ABRT is read. Once
this read is performed, the TX FIFO is then ready to accept
more data bytes from the APB interface.
5
R
RD_REQ
This bit is set to 1 when I2C Ctrl is acting as a slave and
another I2C master is attempting to read data from the con-
troller. The controller holds the I2C bus in a wait state
(SCL=0) until this interrupt is serviced, which means that the
slave has been addressed by a remote master that is asking
for data to be transferred. The processor must respond to
this interrupt and then write the requested data to the
I2C_DATA_CMD register. This bit is set to 0 just after the
processor reads the I2C_CLR_RD_REQ register
0x0
4
R
TX_EMPTY
This bit is set to 1 when the transmit buffer is at or below the
threshold value set in the I2C_TX_TL register. It is automati-
cally cleared by hardware when the buffer level goes above
the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO
is flushed and held in reset. There the TX FIFO looks like it
has no data within it, so this bit is set to 1, provided there is
activity in the master or slave state machines. When there is
no longer activity, then with ic_en=0, this bit is set to 0.
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
103 of 155
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