DM9016
3-port switch with Processor Interface
6.1 Network Control Register (00H)
Bit
7
6
Name
RESERVED
WAKEEN
Default
0,RO
Description
Reserved
PH0,WO Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clear all
wakeup event status
This bit will not be affected after a software reset
5
CLR1
PH0,RW 0: REG. 01H auto-cleared after read
1: REG. 01H cleared by writing 1 to respected bit.
4:2
1
RESERVED
LBK
0,RO
PH0,
RW
Reserved
Loopback Test Mode
0
RST
PH0,RW Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
7:6
Name
RESERVED
Default
0,RO
Description
Reserved
PH0,
W/C1
Link Change Status.
This bit is set after port 0 or 1 link changed. This bit is cleared by write 1
5
LINK_X_ST
RESERVED
TX2END
0,RO
PHS0,
RW/C1
Reserved
TX Packet 2 Complete Status.
This bit is set after transmit completion of packet index 2
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
4
3
2
TX1END
PHS0,
TX Packet 1 Complete status.
RW/C1
This bit is set after transmit completion of packet index 1
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
1:0
RESERVED
0,RO
Reserved
6.3 TX Control Register (02H)
Bit
7:4
3
2
1
Name
RESERVED
CRC_DIS2 PHS0,RW
RESERVED 0,RO
CRC_DIS1 PHS0,RW
TXREQ
Default
0,RO
Description
Reserved
CRC Appends Disable for Packet Index 2
Reserved
CRC Appends Disable for Packet Index 1
0
PHS0,RW TX Request. Auto clears after transmit completely
6.4 RX Control Register (05H)
Bit
7
6
Name
Default
Description
HASHALL PHS0,RW Filter All address in Hash Table
RESERVED PHS0,RW Reserved
5
RESERVED PHS0,RW Reserved
4
3
DIS_CRC
ALL
PHS0,RW Discard CRC Error Packet
PHS0,RW Pass All Multicast Packets
2
RESERVED PHS0,RW Reserved
1
0
PRMSC
RXEN
PHS0,RW Promiscuous Mode
PHS0,RW RX Enable
Preliminarydatasheet
DM9016-13-DS-P01
March 26, 2009
23
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
