DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
Command Register Definition:
15
10
9
8
7
6
5
4
3
2
1
0
Reserved
R/W
0
0
0
0
0
R/W R/W
R/W
R/W
Mast Mode Fast Back-To-Back
SERR# Driver Enable/Disable
Address/Data Steeping
Parity Error Response Enable/Disable
VGA Palette snoop
Memory Write and Invalid
Special Cycle
Master Device Capability Enable/Disable
Memory Space Access Enable/Disable
I/O Space Access Enable/Disable
Bit
15:10
9
Default
000000
0
Type
RO
RO
Description
Reserved
Master Fast Back-to-back Mode (0 For No Support)
The DM6588 does not support master mode fast back-to-back capability
and will not generate fast back-to-back cycles.
SERR# Driver Enable/Disable
8
0
RW
This bit controls the assertion of SERR# signal output. The SERR# output
will be asserted on detection of an address parity error and if both this bit
and bit 6 are set.
7
6
0
0
RO
RW
Address/Data Stepping (0 For No Stepping)
Parity Error Response Enable/Disable
Setting this bit will enable the DM6588 to assert PERR# on the detection of
a data parity error and to assert SERR# for reporting address parity error.
VGA Palette Snooping (0 For No Support)
Memory Write and Invalid (0 For No Support)
Special Cycles (0 For No Implementation)
5
4
3
2
0
0
0
0
RO
RO
RO
RW
Master Device Capability Enable/Disable
The DM6588 will never support the function.
1
0
RW
Memory Space Access Enable/Disable
The DM6588 will never support the function.
0
1
RW
I/O Space Access Enable/Disable
This bit controls the ability of I/O space access.
Final
27
Version: DM562P-DS-F01
February 02, 2004
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
