DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
Bit
Default
Type
Description
31
0
R/C
Detected Parity Error
The DM6588 samples the AD[0:31], C/BE[0:3]#, and the PAR
signal to check parity and to set parity errors.
30
0
R/C
Signaled System Error
This bit is set when the SERR# signal is driven by the
DM6588. This system error occurs when an address parity is
detected under the condition that bit 8 and bit 6 in command
register below are set.
29
28
0
0
R/C
R/C
RO
RO
Master Abort Detected
The DM6588 will never support the function
Target Abort Detected
The DM6588 will never support the function
Send Target Abort (0 For No Implementation)
The DM6588 will never support the function.
DEVSEL Timing (10 Select Slow Timing)
Slow timing of DEVSEL# means the DM6588 will assert
DEVSEL# signal two clocks after FRAME# is sample
“asserted.”
27
0
26:25
10
24
23
0
0
R/C
RO
Data Parity Error Detected
The DM6588 will never support the function
Slave mode Fast Back-To-Back Capable (1 For Good
Capability)
The DM6588 will never support the function
22
0
RO
User-Definable-Feature Supported
(0 For No Support)
21
20
0
1
RO
RO
66 MHz Capable (0 For No Capability)
New Capabilities
_WR
This bit indicates whether this function implements a list of
extended capabilities such as PCI power management. When
set this bit indicates the presence of New Capabilities. A value
of 0 means that this function does not implement New
Capabilities.
19:16
0000
RO
Reserved
26
Final
Version: DM562P-DS-F01
February 02, 2004
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
