DS3251/DS3252/DS3253/DS3254
4. BLOCK DIAGRAMS
Figure 4-1. CPU Bus Mode Block Diagram
RLOSn
T3MCLK E3MCLK STMCLK
VDD
Digital LOS
Detector
PRBS
Clock
Power
Supply
TCLKn
Detector
PRBSn
Adapter
VSS
master clock
B3ZS/HDB3
Decoder
RTSn
Automatic
Gain
RXPn
RXNn
RPOSn/RDATn
Output
Control
+
Clock &
Data
RNEGn/RLCVn
Drivers,
RCLKn
Clock
Adaptive
Equalizer
Recovery
Invert
Remote
ALOS
Loopback
squelch
Digital
Analog
Local
Local
CPU Bus
Loopback
CPU Bus I/O
(see detailed
views below)
Loopback
Interface
and
Global
Configuration
TDMn
Driver
Monitor
TPOSn/TDATn
TNEGn
TCLKn
TXPn
TXNn
Clock
Invert
B3ZS/
HDB3
Encoder
AIS, 100100…,
PRBS Pattern
Generation
Loopback Control
TTSn
PARALLEL INTERFACE
SPI INTERFACE
HIZ
HIZ
RST
RST
HW = 0
HW = 0
CPU Bus
Interface
and
CPU Bus
Interface
and
MOT
ALE
CS
CS
SCLK
Global
Global
SDI
WR / R/W
RD / DS
A[5:0]
D[7:0]
INT
Configuration
Configuration
SDO
CPHA
CPOL
INT
Dallas
MOT=0, WR=0, RD=0
Semiconductor
DS325x
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DALLAS [ DALLAS SEMICONDUCTOR ]
