DS2406
Memory Function Flow Chart (continued) Figure 7
From Figure 7
2nd Part
F5h
Channel
Access
?
AAh
Read Status
N
N
?
Y
Y
Bus Master TX Ch.-
Control Bytes 1, 2
Bus Master TX
TA1(T7:T0), TA2 (T15:T8)
Bus Master TX
Reset Pulse
Bus Master RX
Channel Info Byte
DS2406 sets Status
Address = (T15:T0)
DS2406 TX
Presence Pulse
Y
Master
TX Reset ?
Bus Master RX Data
from Status Memory
N
DS2406
increments
Address
Counter
Y
Master
TX Reset ?
Bus Master
TX Data to
Channel F/F
Write
Read
*
Bus Master
RX Data
*
Access
Mode ?
from PIOs
N
N
End of
Status Mem.
?
Y
Master
TX Reset ?
* See Channel
Control Byte 1
and Figure 7A
Y
Master
TX Reset ?
Y
N
N
CRC*
Enabled ?
N
R
Bus Master RX CRC16 of
Command, Address, Data
Y
S
N
CRC Due * ?
Y
Master
TX Reset ?
Bus Master
RX "1"s
DS2406
increments
CRC Byte
Counter
Y
Y
Master
TX Reset ?
N
N
Bus Master RX CRC16 of Command,
Control, Data (1st pass)
CRC16 of Data (subsequent passes)
Y
Master
TX Reset ?
N
DS2406 clears
CRC Byte Counter
Y
DS2406 toggles
R/W Mode
R/W Toggle
Enabled ?
N
DS2406 TX
Presence Pulse
Vertical
Spare
12 of 31
DALLAS [ DALLAS SEMICONDUCTOR ]
