38
8Bit Single Chip Microcontroller
DMC73C168
IOCTL2
P1 >0102
0 = INTn Inactive
1 = INTn Pending
Read
INT7
FLAG
INT7
ENABL
INT6
ENABL
INT4
ENABL
INT6
FLAG
INT4
FLAG
INT5
FLAG
INT5
ENABL
O
O
O
O
O
O
O
O
Bit
7
6
5
4
3
2
1
0
Write
INT7
ENABL
INT7
CLEAR
INT6
ENABL
INT4
ENABL
INT5
ENABL
INT6
CLEAR
INT5
CLEAR
X
0 = No effect
0 = INTn disable
1 = INTn enable
1 = Clear INTn flag
Figure 5-3C I/O Control Register 2 (IOCTL2)
5.4 Interrupt Logic and External Interrupt
The internal interrupt logic for each eight maskable interrupt of DMC73C168 is shown in Figure 5-4A-1,
54A-2. This interrupt logic will detect the output of each corresponding interrupt and latch the interrupt
Flag.
INTn
INTn
Write
Read
FLAG
ACKNOWLEDGE
Enable Latch
OR
D
Q
INTn
Input
CLR
D
Q
AND
INTn
Happen
Interrupt FLAG
FLAG READ
Interrupt Enable
(Status Register)
Figure 5-4A-1. Interrupt Logic
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