34
8Bit Single Chip Microcontroller
DMC73C168
Level
Name
Trigger Factor
Vector
LSB
MSB
4-1
5
INT4 A/D Converter
INT5 SI/O 1
End of A/D Conversion
End of SI/O 1 Frame
Timer 2 through '>0000"
End of SI/O 2 Frame
>FFF4 >FFF5
>FFF2 >FFF3
>FFF0 >FFF1
6
INT6 Timer 2
INT7 SI/O 2
7
Table 4-8. Interrupt and Reset Priorities
ADDRESS
ADDRESS
>FFD0
>FFD1
/
TRAP23 (A8 - A15)
TRAP23 (A0 - A7)
/
>FFF6
>FFF7
>FFF8
>FFF9
>FFFA
>FFFB
>FFFC
>FFFD
>FFFE
>FFFF
INT4, A/D OR TRAP4 (A8-A15)
INT4, A/D OR TRAP4 (A0-A7)
INT3 OR TRAP3 (A8-A15)
INT3 OR TRAP3 (A0-A7)
/
/
/
/
TIMER1 OR TRAP2 (A8-A15)
TIMER1 OR TRAP2 (A0-A7)
INT1 OR TRAP1 (A8-A15)
INT1 OR TRAP1 (A0-A7)
>FFF0
>FFF1
>FFF2
>FFF3
>FFF4
>FFF5
SI/O2 OR TRAP7 (A8-A15)
SI/O2 OR TRAP7 (A0-A7)
TIMER2 OR TRAP6 (A8-A15)
TIMER2 OR TRAP6 (A0-A7)
SI/O1 OR TRAP5 (A8-A15)
SI/O1 OR TRAP5 (A0-A7)
RESET OR TRAP0 (A8-A15)
RESET OR TRAP0 (A0-A7)
Figure 4-8. The TRAP Vector Table
5. DESCRIPTION OF EACH FUNCTION
5.1 Input / Output Ports
DMC73C168 has 64 I/O pins organized as eight parallel ports labeled Port A,B,C,D,E,F,G,H each Port
is mapped 8 bit data value register in the Peripheral File (PF). The data value registers are usually
called APORT, BPORT, CPORT, DPORT, EPORT, FPORT, GPORT and HPORT in a program.
All Ports are implemented as bidirectional I/O Ports.
Each Bidirecitional ports has a corresponding 8 bit Data Direction Register (DDR) that programs each
ports as input or output. A bit set to one in the DDR will cause the corresponding pin to be an output,
while a zero in the DDR will cause the pin to be a high impedance input.
Upon RESET, the DDR file-flop register are set to zero by the on-chip circuitly, forcing them to become
inputs. And output data register ports (A,B,C,D,E,F,G and H) are indeterminate data set. After RESET,
if '1' s are written to the DDR register sometime before the output data register is changed then the
corresponding I/O pins will output a "1". For this reason, it is good practice that ports A,B,C,D,E,F,G,H
output data register is loaded with the desired value before any bits are configured as outputs.
The logic for each bidirectional I/O line is shown in Figure 5-1.
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