36
8Bit Single Chip Microcontroller
DMC73C168
5.2 Device Initialization
Interrupt level 0 (RESET) cannot be masked and will be recognized immediately even in the middle of
instruction. To execute the level 0 interrupt, the RESET pin must be held low for minimum of 5 internal
clock cycles to guarantee recognition by the device. During assertion of the RESET pin, the following
operations are performed prior to the first instruction acquisition.
1) All zeros are written to the IOCTL0 Register and Status Register. And zero is written to the
IOCTL1, and IOCTL2. This disables all interrupt and clears all interrupt flags.
2) The initialize data are written to the Peripheral Registers. And all zeros are written to the
APSLCT, ADDR, BDDR, CDDR, DDDR, EDDR, FDDR, GDDR and HDDR.
3) The MSB and LSB values of the Program Counter Just before RESET are stored in R0 and
R1 (A and B Register) respectively.
4) The Stack Pointer is initialized to >01.
5) The MSB and LSB of the Reset Vector are fetched location >FFFE and >FFFF respectively
(see Table 4-8) and loaded into the Program Counter.
6) Program execute begins from the address placed in the Program Counter.
5.3 I/O Control Register
The I/O control register are located in the Peripheral File and are responsible for interrupt control.
The DMC73C168 contains the I/O Control 0 (IOCTL0), I/O Control 1 (IOCTL1), I/O Control 2 (IOCTL2).
The I/O control register are mapped into locations P0 (IOCTL0), P1 (IOCTL1), P2 (IOCTL2) of the
Peripheral File as shown in Figure 5-3A, 5-3B and 5-3C. The individual interrupt mask and resets are
controlled through these registers. The interrupt sources may also be individually tested by reading the
interrupt flags. The interrupt flag values are independent of the interrupt enable values. The INTn FLAG
values are independent of the INTn ENABLE values. Writing a '1' to the INTn CLEAR bit will clear the
corresponding INTn FLAG, but writing a '0' to the INTn CLEAR bit has no effect on the bit. If INTn is to
be recognized by the CPU, three conditions must be met as follow.
1) A one must be written to the INTn ENABLE BIT IN THE IOCTL0, IOCTL1 or IOCTL2
Register.
2) The global INTERRUPT ENABLE bit, IE., bit4 in the Status Register, must be set to one
by the EINT instruction.
3) INTn must be the highest priority interrupt asserted within an instruction boundary.
Setting '1' to both INTnFLAG and INTnENABLE bit clears the INTnFLAG first, and then sets '1' to
INTnENABLE bit.
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