W134M/W134S
Timing Diagrams
Power-down Exit and Entry
PwrDnB
Clk/ClkB
t
t
POWERDN
POWERUP
Output Enable Control
t
ON
t
STOP
t
StopB
CLKON
t
CLKOFF
t
CLKSETL
Clk/ClkB
Output clock
not specified
glitches may
occur
Clock output settled within
50 ps of the phase before
disabled
Clock enabled
and glitch-free
Figure 5. State Transition Timing Diagrams
Mult0 and/or Mult1
Clk/ClkB
tMULT
Figure 6. Multiply Transition Timing
Table 8. State Transition Latency Specifications
Transition Latency
Transition
From
To
Parameter
Max.
Description
A
Power-down
Normal
tPOWERUP
3 ms
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
C
K
G
H
M
J
Power-down
Power-down
Clk Stop
Test
tPOWERUP
tPOWERUP
tPOWERUP
tPOWERUP
tPOWERUP
tMULT
3 ms
3 ms
3 ms
3 ms
3 ms
1 ms
Time from PwrDnB until the internal PLL and clock has
turned ON and settled.
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
VDD ON
VDD ON
VDD ON
Normal
Clk Stop
Test
Time from VDD is applied and settled until Clk/ClkB
output settled (excluding tDISTLOCK).
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
Time from VDD is applied and settled until internal PLL
and clock has turned ON and settled.
Normal
Normal
Time from when Mult0 or Mult1 changed until Clk/ClkB
output resettled (excluding tDISTLOCK).
Document #: 38-07426 Rev. *B
Page 6 of 12
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