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SL811HST 参数 Datasheet PDF下载

SL811HST图片预览
型号: SL811HST
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式USB主/从控制器 [Embedded USB Host/Slave Controller]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输PC时钟
文件页数/大小: 29 页 / 499 K
品牌: CYPRESS [ CYPRESS ]
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SL811HS  
5.2.4  
SOF Packet Generation  
The SL811HS automatically computes CRC5 by hardware. No CRC or SOF is required to be generated by external firmware for  
SL811HS.  
5.2.5  
USB-A/USB-B Host Base Address [01H, 09H]  
The USB-A/USB-B Base Address is a Pointer to the SL811HS memory buffer location for USB reads and writes. When trans-  
ferring data OUT (Host to Device), the USB-A and USB-B can be set up prior to setting ARM on the USB-A or USB-B Host Control  
register. See the software implementation example.  
5.2.6  
USB-A/USB-B Host Base Length [02H, 0AH]  
The USB A/B host base register contains the maximum packet size to be transferred between the SL811HS and a slave USB  
peripheral. Essentially, this designates the largest packet size that can be transferred by the SL811HS. Base Length designates  
the size of data packet to be sent. For example, in Bulk mode the maximum packet length is 64 bytes. In ISO mode, the maximum  
packet length is 1023, since the SL811HS only has an 8-bit length; the maximum packet size for the ISO mode using the SL811HS  
is 255 16 bytes. When the Host Base Length register is set to zero, a Zero-Length packet will be transferred.  
5.2.7  
USB-A/USB-B Host PID, Device Endpoint (Write)/USB Status (Read) [03H, 0BH]  
This register has two modes. When read, this register provides packet status and it contains information relative to the last packet  
that has been received or transmitted. The register is defined as follows.  
Bit Position  
Bit Name  
ACK  
Function  
0
1
2
3
4
5
6
7
Transmission Acknowledge  
Error detected in transmission  
Time-out occurred  
Error  
Time-out  
Sequence  
Setup  
Sequence Bit. 0if DATA0, 1if DATA1  
1indicates Setup Packet  
Overflow  
NAK  
Overflow condition - maximum length exceeded during receives  
Slave returns NAK  
STALL  
Slave set STALL bit  
When written, this register provides the PID and Endpoint information to the USB SIE engine to be used in the next transaction.  
All sixteen Endpoints can be addressed by the SL811HS.  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
PID3  
PID2  
PID1  
PID0  
EP3  
EP2  
EP1  
EP0  
PID3-0  
EP3-0  
4-bit PID Field (See Table Below)  
4-bit Endpoint Value in Binary.  
PID TYPE  
D7-D4  
SETUP  
IN  
1101 (D Hex)  
1001 (9 Hex)  
OUT  
0001 (1 Hex)  
0101 (5 Hex)  
1100 (C Hex)  
1010 (A Hex)  
1110 (E Hex)  
0011 (3 Hex)  
1011 (B Hex)  
SOF  
PREAMBLE  
NAK  
STALL  
DATA0  
DATA1  
Document #: 38-08008 Rev. *A  
Page 11 of 29  
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