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SL811HST 参数 Datasheet PDF下载

SL811HST图片预览
型号: SL811HST
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式USB主/从控制器 [Embedded USB Host/Slave Controller]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输PC时钟
文件页数/大小: 29 页 / 499 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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SL811HS
4.7.1
Typical Crystal Requirements
The following are examples of “typical requirements”. Please note that these specifications are generally found as standard crystal
values and are therefore less expensive than custom values. If crystals are used in series circuits, load capacitance is not
applicable. Load capacitance of parallel circuits is a requirement.
12-MHz Crystals:
Frequency Tolerance:
Operating Temperature Range:
Frequency:
Frequency Drift over Temperature:
ESR (Series Resistance):
Load Capacitance:
Shunt Capacitance:
Drive Level:
Operating Mode:
±100 ppm or better
0°C to 70°C
12 MHz
± 50 ppm
60Ω
10 pF min.
7 pF max.
0.1–0.5 mW
fundamental
48-MHz Crystals:
Frequency Tolerance:
Operating Temperature Range:
Frequency:
Frequency Drift over Temperature:
ESR (Series Resistance):
Load Capacitance:
Shunt Capacitance:
Drive Level:
Operating Mode:
±100 ppm or better
0°C to 70°C
48 MHz
± 50 ppm
40
10 pF min.
7 pF max.
0.1–0.5 mW
third overtone
4.8
USB Transceiver
The SL811HS has a built in transceiver that meets USB Specification 1.1. The transceiver is capable of transmitting and receiving
serial data at USB full speed (12 Mbits) and low speed (1.5 Mbits). The driver portion of the transceiver is differential while the
receiver section is comprised of a differential receiver and two single-ended receivers. Internally, the transceiver interfaces to the
Serial Interface Engine (SIE) logic. Externally, the transceiver connects to the physical layer of the USB.
5.0
SL811HS Registers
Operation of the SL811HS is controlled through 16 internal registers. A portion of the internal RAM is devoted to the control
register space, and access is through the microprocessor interface. The registers provide control and status information for
transactions on the USB, microprocessor interface, and interrupts.
Any Write to control register 0FH will enable the SL811HS full features bit. This is an internal bit of the SL811HS that enables
additional features not supported by the SL11H. For SL11H hardware backward compatibility, this register should not be
accessed.
The table below shows the memory map and register mapping of both the SL11H and SL811HS. The SL11H is shown for users
upgrading to the SL811HS.
Document #: 38-08008 Rev. *A
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