PSoC® 3: CY8C32 Family
Data Sheet
Figure 5-2. 8051 Internal Data Space
In addition to the register or bit address modes used with the
lower 48 bytes, the lower 128 bytes can be accessed with direct
or indirect addressing. With direct addressing mode, the upper
128 bytes map to the SFRs. With indirect addressing mode, the
upper 128 bytes map to RAM. Stack operations use indirect
addressing; the 8051 stack space is 256 bytes. See the
“Addressing Modes” section on page 11
0x00
4 Banks, R0-R7 Each
0x1F
0x20
0x2F
0x30
Bit-Addressable Area
Lower Core RAM Shared with Stack Space
(direct and indirect addressing)
0x7F
0x80
SFR
Upper Core RAM Shared
with Stack Space
(indirect addressing)
Special Function Registers
(direct addressing)
0xFF
5.7.3 SFRs
The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory
space is shown in Table 5-4.
Table 5-4. SFR Map
Address
0×F8 SFRPRT15DR
0×F0
0/8
1/9
2/A
SFRPRT15SEL
SFRPRT12SEL
MXAX
3/B
4/C
5/D
6/E
7/F
SFRPRT15PS
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
B
–
0×E8 SFRPRT12DR
0×E0 ACC
SFRPRT12PS
–
–
0×D8 SFRPRT6DR
0×D0 PSW
SFRPRT6PS
SFRPRT6SEL
–
–
0×C8 SFRPRT5DR
0×C0 SFRPRT4DR
SFRPRT5PS
SFRPRT5SEL
SFRPRT4SEL
–
SFRPRT4PS
0×B8
–
–
0×B0 SFRPRT3DR
0×A8 IE
SFRPRT3PS
SFRPRT3SEL
–
–
0×A0 P2AX
–
SFRPRT1SEL
SFRPRT2SEL
–
0×98 SFRPRT2DR
0×90 SFRPRT1DR
SFRPRT2PS
SFRPRT1PS
SFRPRT0PS
SP
DPX0
–
DPX1
–
0×88
–
SFRPRT0SEL
DPL0
–
0×80 SFRPRT0DR
DPH0
DPL1
DPH1
DPS
The CY8C32 family provides the standard set of registers found
on industry standard 8051 devices. In addition, the CY8C32
devices add SFRs to provide direct access to the I/O ports on the
device. The following sections describe the SFRs added to the
CY8C32 family.
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
XData Space Access SFRs
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1.
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
During a MOVX instruction using the R0 or R1 register, the most
significant byte of the address is always equal to the contents of
MXAX, and the next most significant byte is always equal to the
contents of P2AX.
Document Number: 001-56955 Rev. *J
Page 25 of 119
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