CY7C9689
CY7C9689 Receiver TTL Switching Characteristics, FIFO Bypassed Over the Operating Range
Parameter
Description
Min.
Max.
Unit
[20]
f
RXCLK Clock Output Frequency—100 to 200 MBaud 8-bit Operation
10
20
MHz
ROS
(SPDSEL is HIGH and BYTE8/10 is HIGH)
RXCLK Clock Output Frequency—50 to 100 MBaud 8-bit Operation
(SPDSEL is LOW and BYTE8/10 is HIGH)
5
10
MHz
MHz
MHz
RXCLK Clock Output Frequency—100 to 200 MBaud 10-bit Operation
(SPDSEL is HIGH and BYTE8/10 is LOW)
8.33
4.16
16.67
8.33
RXCLK Clock Output Frequency—50 to 100 MBaud 10-bit Operation
(SPDSEL is LOW and BYTE8/10 is LOW)
t
t
t
t
t
t
t
RXCLK Output Period
25
40
0.25
0.25
4
240
60
2
ns
%
RXCLKOP
RXCLK Output Duty Cycle
RXCLKOD
[16]
[18]
RXCLK Output Rise Time
ns
ns
ns
ns
ns
RXCLKOR
[16]
[18]
RXCLK Output Fall Time
2
RXCLKOF
Receive Enable Set-Up Time to RXCLK↑
Receive Enable Hold Time from RXCLK↑
RXENS
RXENH
RXZA
1
Sample of CE LOW by RXCLK↑, Outputs High-Z to Active
Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs High-Z to Active
0
t
Sample of CE LOW by RXCLK↑ to Flag Output Valid
Sample of RXEN Asserted by RXCLK↑ to RXDATA Output Low-Z
1.5
1.5
20
20
ns
ns
RXOE
RXAZ
t
Sample of CE HIGH by RXCLK↑ to Flag Output High-Z
Sample of RXEN Deasserted by RXCLK↑ to RXDATA Output High-Z
CY7C9689 REFCLK Input Switching Characteristics Over the Operating Range
Conditions
Parameter
Description
SPDSEL RANGESEL BYTE8/10 Min.
Max.
Unit
f
REFCLK Clock Frequency—50 to 100 MBaud,
10-bit Mode, REFCLK = 2x Character Rate
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
8.33
16.67 MHz
REF
REFCLK Clock Frequency—50 to 100 MBaud,
8-bit Mode, REFCLK = 2x Character Rate
0
10
20
33.3
40
MHz
MHz
MHz
[21]
REFCLK Clock Frequency—50 to 100 MBaud,
10-bit Mode, REFCLK = 4x Character Rate
1
1
16.67
20
[21]
REFCLK Clock Frequency—50 to 100 MBaud,
8-bit Mode, REFCLK = 4x Character Rate
REFCLK Clock Frequency—100 to 200 MBaud,
10-bit Mode, REFCLK = Character Rate
0
0
1
1
8.33
10
16.67 MHz
REFCLK Clock Frequency—100 to 200 MBaud,
8-bit Mode, REFCLK = Character Rate
20
33.3
40
MHz
MHz
MHz
REFCLK Clock Frequency—100 to 200 MBaud,
10-bit Mode, REFCLK = 2x Character Rate
16.67
20
REFCLK Clock Frequency—100 to 200 MBaud,
8-bit Mode, REFCLK = 2x Character Rate
t
t
t
t
REFCLK Period
25
6.5
120
ns
ns
ns
%
REFCLK
REFCLK HIGH Time
REFCLK LOW Time
REFH
6.5
REFL
[22]
REFCLK Frequency Referenced to Received Clock Period
−0.04
+0.04
REFRX
Notes:
20. The period of tROS will match the period of the transmitterPLL reference (REFCLK) when receiving serialdata. When data isinterrupted, RXCLK maydrift to REFCLK +0.2%.
21. When configured for synchronous operation with the FIFOs bypassed (FIFOBYP is LOW), if RANGESEL is HIGH the SPDSEL input is ignored and operation
is forced to the 100–200 MBaud range.
22. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
within ±0.04% of the transmitter PLL reference (REFCLK) frequency, necessitating a ±200-PPM crystal.
25
CYPRESS [ CYPRESS ]
