CY7C9689
Pin Descriptions
(continued)
Pin
Name
I/O Characteristics
PECL compatible
differential output
Signal Description
Differential Serial Data Outputs.
These PECL-compatible differential outputs are capable of driving terminated
transmission lines or commercial fiber-optic transmitter modules. To minimize
the power dissipation of unused outputs, the outputs should be left unconnected
and the associated CURSETA or CURSETB should be connected to V
DD
.
Differential Serial Data Inputs.
These inputs accept the serial data stream for deserialization and decoding.
Only one serial stream at a time may be fed to the receive PLL to extract the
data content. This stream is selected using the A/B input.
Current-set Resistor Input for OUTA±.
A precision resistor is connected between this input and a clean ground to set
the output differential amplitude and currents for the OUTA± differential driver.
78
CURSETB
Analog
Current-set Resistor Input for OUTB±.
A precision resistor is connected between this input and a clean ground to set
the output differential amplitude and currents for the OUTB± differential driver.
100
CARDET
PECL input,
asynchronous
Carrier Detect Input.
Used to allow an external device to signify a valid signal is being presented to
the high-speed PECL input buffers, as is typical on an Optical Module. When
CARDET is deasserted LOW, the LFI indicator asserts LOW signifying a Link
Fault. This input can be tied HIGH for copper media applications.
Input A or Input B Selector.
When HIGH, input INA± is selected, when LOW, INB± is selected.
Analog I/O and Control
89, 90, OUTA±
81, 82 OUTB±
94, 93, INA±
86, 85 INB±
PECL compatible
differential input
97
CURSETA
Analog
2
3
A/B
LFI
Asynchronous
TTL input
Three-state TTL out- Link Fault Indication Output. Active LOW.
put, changes following LFI changes synchronous with RXCLK. This output is driven LOW when the
RXCLK¦
serial link currently selected by A/B is not suitable for data recovery. This could
be because:
1. Serial Data Amplitude is below acceptable levels
2. Input transition density is not sufficient for PLL clock recovery
3. Input Data stream is outside an acceptable frequency range of operation
4. CARDET is LOW
5
DLB
Asynchronous
TTL input
Diagnostic Loop Back Selector.
When DLB is LOW, LOOP Mode is OFF. Output of the transmitter shifter is
routed to both OUTA± and OUTB± and the serial input selected by A/B is routed
to the receive PLL for data recovery.
When DLB is HIGH, Diagnostic Loopback is Enabled. Output of the transmitter
serial data is routed to the receive PLL for data recovery. Primarily used for
System Diagnostic test. The serial inputs are ignored and OUTA± and OUTB±
are both active.
1
TEST
Asynchronous
TTL input normally
wired HIGH
Test Mode Select.
Used to force the part into a diagnostic test mode used for factory ATE test. This
input must be tied HIGH during normal operation.
Power for PECL-compatible I/O signals and internal circuits.
Power
80, 87, V
DDA
88, 95,
96, 98
76, 79, V
SSA
83, 84,
91, 92,
99
Ground for PECL-compatible I/O signals and internal circuits.
12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
