CY7C9689
Pin Descriptions (continued)
Pin
28
Name
I/O Characteristics
Signal Description
FIFOBYP
Static control input
TTL levels
Normally wired HIGH
or LOW
FIFO Bypass Enable.
When asserted, the Transmit and Receive FIFOs are bypassed. In this mode
TXCLK is not used. Instead all transmit data must be synchronous to REFCLK.
Transmit FIFO status flags are synchronized to REFCLK. All received data is
synchronous to RXCLK output. Receive FIFO status flags are synchronized to
RXCLK (the recovered Receive PLL character clock).
When not asserted, the Transmit and Receive FIFOs are enabled. In this mode
all Transmit FIFO writes are synchronized to TXCLK, and all Receive FIFO
reads are synchronous to the RXCLK input.
50
BYTE8/10
Static control input
TTL levels
8/10-bit Parallel Data Size Select.
When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is enabled
(ENCBYP is HIGH), 8-bit DATA characters and 4-bit COMMAND characters are
captured at the TXDATA[7:0] or TXCMD[3:0] inputs (selected by the TXSC/D
input) and passed to the Transmit FIFO (if enabled) and encoder. Received
characters are decoded, passed through the Receive FIFO (if enabled) and
presented at either the RXDATA[7:0] or RXCMD[3:0] outputs and indicated by
the RXSC/D output.
Normally wired HIGH
or LOW
When set for 8-bit data (BYTE8/10 is HIGH) and the encoder is bypassed
(ENCBYP is LOW), the internal data paths are set for 10-bit characters. Each
received character is presented to the Receive FIFO (if enabled) and is passed
to the RXDATA[9:0] outputs.
When set for 10-bit data (BYTE8/10 is LOW) and the encoder is enabled
(ENCBYP is HIGH), 10-bit DATA characters and 2-bit COMMAND characters
are captured at the TXDATA[9:0] or TXCMD[1:0] inputs (selected by the TXSC/D
input) and passed to the Transmit FIFO (if enabled) and encoder. Received
characters are decoded, passed through the Receive FIFO (if enabled) and
presented at either the RXDATA[9:0] or RXCMD[1:0] outputs and indicated by
the RXSC/D output.
When set for 10-bit data (BYTE8/10 is LOW) and the encoder is bypassed
(ENCBYP is LOW), the internal clock data paths are set for 12-bit characters.
Each received character is presented to the Receive FIFO (if enabled) and is
passed to the RXDATA[9:0] and the RXCMD[1:0] outputs.
49
EXTFIFO
Static control input
TTL levels
External FIFO Mode.
EXTFIFO modifies the active state of the RXEN and TXEN inputs and the timing
of the Transmitter and Receiver data buses. When configured for external FIFOs
(EXTFIFO is HIGH), TXEN is assumed to be driven by the empty flag of an
attached CY7C42X5 FIFO, and RXEN is assumed to be driven by the almost
full flag of an attached CY7C42X5 FIFO. In this mode the active data transition
is in the clock following the clock edge that “enables” the data bus.
Normally wired HIGH
or LOW
When not configured for external FIFOs (EXTFIFO is LOW), TXEN is assumed
to be driven as a pipeline register and RXEN is assumed to be driven by a
controller for a pipeline register. In this mode the active data transition is within
the same clock as the clock edge that “enables” the data bus.
EXTFIFO also modifies the output state of the Receive and Transmit FIFO flags.
When configured for external FIFOs (EXTFIFO is HIGH), the Full and Empty
FIFO flags are active HIGH (the Half full flag is always active LOW). When not
configured for external FIFOs (EXTFIFO is LOW), all of the FIFO flags are active
LOW.
27
ENCBYP
Static control input
TTL levels
Normally wired HIGH
or LOW
Enable Encoder Bypass Mode.
When asserted, both the encoder and decoder are bypassed. Data is transmit-
ted without 4B/5B or 5B/6B encoding (but with NRZI encoding), LSB first. Re-
ceived data are presented as parallel characters to the parallel interface without
decoding.
When deasserted, data is passed through both the encoder in the Transmit path
and the decoder in the Receive path.
11
CYPRESS [ CYPRESS ]
