CY7C9689
Pin Descriptions
(continued)
Pin
71
CE
Name
I/O Characteristics
Signal Description
Control Signals
TTL input sampled on Chip Enable Input. Active LOW.
TXCLK¦, RXCLK¦, or When CE is asserted and sampled LOW by RXCLK, the Receive FIFO status
REFCLK¦
flags are driven to their active states. When this input is deasserted and sampled
by RXCLK, the Receive FIFO status flags are placed in a High-Z state.
When CE has been sampled LOW and RXEN changes from deasserted to
asserted and is sampled by RXCLK, the RXSC/D, RXDATA[7:0], RXDATA[9:8]/
RXCMD[2:3] and VLTN output drivers are enabled and go to their driven levels.
These pins remain driven until RXEN is sampled deasserted.
When the Transmit FIFO is enabled (FIFOBYP is HIGH), and CE is asserted
and sampled by TXCLK, the Transmit FIFO status flags are driven to their active
states. When this input is deasserted and sampled by TXCLK, the Transmit
FIFO status flags are placed in a High-Z state.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), and CE is asserted
and sampled by REFCLK, the Transmit FIFO status flags are driven to their
active states. When this input is deasserted and sampled by REFCLK, the
Transmit FIFO status flags are placed in a High-Z state.
When the Transmit FIFO is enabled (FIFOBYP is HIGH), CE has been sampled
LOW, and TXEN changes from deasserted to asserted and is sampled by
TXCLK, the TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], and
TXCMD[1:0] inputs are sampled and passed to the Transmit FIFO. These inputs
are sampled on all consecutive TXCLK cycles until TXEN is sampled
deasserted.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), CE has been sampled
LOW, and TXEN changes from deasserted to asserted and is sampled by
REFCLK, the TXSC/D, TXDATA[7:0], TXDATA[9:8]/RXCMD[2:3], and
TXCMD[1:0] inputs are sampled and passed to the encoder or serializer as
directed by other control inputs. These inputs are sampled on all consecutive
REFCLK cycles until TXEN is sampled deasserted.
12
REFCLK
TTL clock input
PLL Frequency Reference Clock.
This clock input is used as the timing reference for the transmit and receive
PLLs. When the Transmit FIFO is bypassed (FIFOBYP is HIGH), REFCLK is
also used as the clock for the parallel transmit interface.
75
SPDSEL
Static control input
TTL levels
Normally wired HIGH
or LOW
Static control input
TTL levels
Normally wired HIGH
or LOW
Speed Select.
Used to select from one of two operating serial rates for the CY7C9689. When
SPDSEL is HIGH, the signaling rate is between 100 and 200 MBaud. When
LOW, the signaling rate is between 50 and 100 MBaud. Used in combination
with RANGESEL and BYTE8/10 to configure the VCO multipliers and dividers.
Range Select.
Selects the proper prescaler for the REFCLK input. If RANGESEL is LOW, the
REFCLK input is passed directly to the Transmit PLL clock multiplier. If
RANGESEL is HIGH, REFLCK is divided by two before being sent to the Trans-
mit PLL multiplier.
When the Transmit FIFO is bypassed (FIFOBYP is LOW), with RANGESEL
HIGH or SPDSEL LOW, TXFULL toggles at half the REFCLK rate to provide a
character rate indication, and to show when data can be accepted.
51
RESET
Asynchronous
TTL input
Master Reset for Internal Logic.
Pulsed LOW for one or more REFCLK cycles.
74
RANGESEL
10
CYPRESS [ CYPRESS SEMICONDUCTOR ]
