CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.16.3 Sequence Diagram of a Single and Burst Asynchronous Read
t
t
t
t
FAH
SFA
SFA
FAH
FIFOADR
t=0
t
t
t
t
RDpwh
t
t
RDpwl
t
t
T=0
RDpwl
RDpwl
RDpwl
RDpwh
RDpwh
RDpwh
SLRD
SLCS
t=3
t=2
T=2
T=3
T=5
T=4
T=6
t
XFLG
t
XFLG
FLAGS
DATA
SLOE
t
t
XFD
t
XFD
XFD
t
XFD
Data (X)
Driven
N+3
N
N+1
N+2
N
t
t
OEon
t
t
OEoff
OEoff
OEon
t=4
T=1
T=7
t=1
Figure 9-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
SLOE
SLRD
SLRD
SLOE
SLOE
SLRD
N+1
SLRD
N+1
SLRD
N+2
SLRD
N+2
SLOE
FIFO POINTER
N
N
N
N
N+1
N
N+1
N+3
N+2
N+3
FIFO DATA BUS Not Driven
Driven: X
Not Driven
N
N+1
N+1
N+2
Not Driven
Figure 9-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
Figure 9-19 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
• The data that will be driven, after asserting SLRD, is the
updated data from the FIFO. This data is valid after a propa-
gation delay of t
from the activating edge of SLRD. In
XFD
Figure 9-19, data N is the firstvalid data read from the FIFO.
For data to appear on the data bus during the read cycle
(i.e. ,SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
• At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
• At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5. Note: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
• At t = 2, SLRD is asserted. The SLRD must meet the
minimum active pulse of t
and minimum de-active
RDpwl
pulse width of t
. If SLCS is used then, SLCS must be
RDpwh
in asserted with SLRD or before SLRD is asserted (i.e., the
SLCS and SLRD signals must both be asserted to start a
valid read condition.)
Document #: 38-08032 Rev. *G
Page 49 of 55
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