CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.16.4 Sequence Diagram of a Single and Burst Asynchronous Write
t
t
t
FAH
t
SFA
SFA
FAH
FIFOADR
t=0
T=0
t
t
t
t
t
t
t
WRpwh
t
WRpwl
WRpwl
WRpwl
WRpwh
WRpwl
WRpwh
WRpwh
SLWR
SLCS
t =1
t=3
T=4
T=1
T=7
T=3
T=6
T=9
t
XFLG
t
XFLG
FLAGS
DATA
t
t
t
t
t
t
t
SFD
t
SFD FDH
SFD FDH
SFD FDH
FDH
N
N+1
N+2
N+3
t=2
T=8
T=2
T=5
t
t
PEpwl
PEpwh
PKTEND
[19]
Figure 9-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram
Figure 9-21 diagrams the timing relationship of the SLAVE
FIFO write in an asynchronous mode. The diagram shows a
single write followed by a burst write of 3 bytes and committing
the 4-byte-short packet using PKTEND.
pointer. The FIFO flag is also updated after t
asserting edge of SLWR.
from the de-
XFLG
The same sequence of events are shown for a burst write and
is indicated by the timing marks of T = 0 through 5. Note: In
the burst write mode, once SLWR is deasserted, the data is
written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
·At t = 0 the FIFO address is applied, insuring that it meets the
set-up time of t
. If SLCS is used, it must also be asserted
SFA
(SLCS may be tied low in some applications).
·..At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
and minimum de-active pulse width of
In Figure 9-21 once the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND
signal at the same time. It should be designed to assert the
PKTEND after SLWR is de-asserted and met the minimum de-
asserted pulse width. The FIFOADDR lines are to be held
constant during the PKTEND assertion.
WRpwl
t
. If the SLCS is used, it must be in asserted with SLWR
WRpwh
or before SLWR is asserted.
·At t = 2, data must be present on the bus t
asserting edge of SLWR.
before the de-
SFD
·At t = 3, de-asserting SLWR will cause the data to be written
from the data bus to the FIFO and then increments the FIFO
Document #: 38-08032 Rev. *G
Page 50 of 55
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