CY7C1470V25
CY7C1472V25
CY7C1474V25
Electrical Characteristics
(continued)
Over the Operating Range
[12, 13]
Parameter
I
SB3
Description
Automatic CE
power-down
current—CMOS inputs
Automatic CE
power-down
current—TTL inputs
Test Conditions
Max V
DD
, device deselected, 4.0-ns cycle, 250 MHz
V
IN
0.3 V or
5.0-ns cycle, 200 MHz
V
IN
> V
DDQ
0.3
V,
f = f
MAX
= 1/t
CYC
6.0-ns cycle, 167 MHz
Max V
DD
, device deselected, All speed grades
V
IN
V
IH
or V
IN
V
IL
, f = 0
Min
–
–
–
–
Max
200
200
200
135
Unit
mA
mA
mA
mA
I
SB4
Capacitance
Parameter
C
ADDRESS
C
DATA
C
CTRL
C
CLK
C
I/O
Description
Address input capacitance
Data input capacitance
Control input capacitance
Clock input capacitance
Input/output capacitance
Test Conditions
T
A
= 25
C,
f = 1 MHz,
V
DD
= 2.5 V
V
DDQ
= 2.5 V
100 TQFP
Max
6
5
8
6
5
165 FBGA 209 FBGA
Max
Max
6
5
8
6
5
6
5
8
6
5
Unit
pF
pF
pF
pF
pF
Thermal Resistance
Parameter
JA
JC
Description
Test Conditions
100 TQFP
Package
24.63
2.28
165 FBGA
Package
16.3
2.1
209 FBGA
Package
15.2
1.7
Unit
C/W
C/W
Thermal resistance Test conditions follow standard
(junction to ambient) test methods and procedures for
Thermal resistance measuring thermal impedance,
per EIA/JESD51.
(junction to case)
Note
15. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05290 Rev. *L
Page 20 of 31
CYPRESS [ CYPRESS SEMICONDUCTOR ]
