CY7C1470V25
CY7C1472V25
CY7C1474V25
Switching Waveforms
(continued)
NOP, STALL and DESELECT Cycles
1
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
2
3
4
5
6
7
8
9
10
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing
CLK
t ZZ
t ZZREC
ZZ
t ZZI
I
SUPPLY
I DDZZ
t RZZI
DESELECT or READ Only
ALL INPUTS
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH,CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05290 Rev. *L
Page 24 of 31
CYPRESS [ CYPRESS SEMICONDUCTOR ]
