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CY7C1470V25-200BZC 参数 Datasheet PDF下载

CY7C1470V25-200BZC图片预览
型号: CY7C1470V25-200BZC
PDF下载: 下载PDF文件 查看货源
内容描述: 72兆位(2M X 36/4的M× 18/1米× 72 )流水线SRAM与NOBL架构 [72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture]
分类和应用: 静态存储器
文件页数/大小: 31 页 / 843 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1470V25
CY7C1472V25
CY7C1474V25
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage on V
DD
relative to GND ........–0.5 V to +3.6 V
Supply voltage on V
DDQ
relative to GND....... –0.5 V to +V
DD
DC to outputs in tri-state ....................–0.5 V to V
DDQ
+ 0.5 V
DC input voltage .................................. –0.5 V to V
DD
+ 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0 °C to +70 °C
V
DD
V
DDQ
2.5 V – 5% / + 1.7 V to V
DD
5%
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
IH
V
IL
I
X
Description
Power supply voltage
I/O supply voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
except ZZ and MODE
Input current of MODE
Input current of ZZ
I
OZ
I
DD
for 2.5 V I/O
for 1.8 V I/O
for 2.5 V I/O, I
OH
=1.0 mA
for 1.8 V I/O, I
OH
= –100
A
for 2.5 V I/O, I
OL
=1.0 mA
for 1.8 V I/O, I
OL
= 100
A
for 2.5 V I/O
for 1.8 V I/O
for 2.5 V I/O
for 1.8 V I/O
GND
V
I
V
DDQ
Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
Output leakage current GND
V
I
V
DDQ,
output disabled
V
DD
operating supply
V
DD
= Max, I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
I
SB1
Automatic CE
power-down
current—TTL inputs
Automatic CE
power-down
current—CMOS inputs
Max V
DD
, device deselected, 4.0-ns cycle, 250 MHz
V
IN
V
IH
or V
IN
V
IL
,
5.0-ns cycle, 200 MHz
f = f
MAX
= 1/t
CYC
6.0-ns cycle, 167 MHz
Max. V
DD
, device deselected, All speed grades
V
IN
0.3 V or
V
IN
> V
DDQ
0.3
V, f = 0
Test Conditions
Min
2.375
2.375
1.7
2.0
1.6
1.7
1.26
–0.3
–0.3
–5
–30
–5
–5
Max
2.625
V
DD
1.9
0.4
0.2
V
DD
+ 0.3 V
V
DD
+ 0.3 V
0.7
0.36
5
5
30
5
450
450
400
200
200
200
120
Unit
V
V
V
V
V
V
V
V
V
V
V
A
A
A
A
A
A
mA
mA
mA
mA
mA
mA
mA
I
SB2
Notes
12. Overshoot: V
IH
(AC) < V
DD
+ 1.5 V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC) > –2 V (Pulse width less than t
CYC
/2).
13. T
Power-up
: Assumes a linear ramp from 0 V to V
DD
(min) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
14. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05290 Rev. *L
Page 19 of 31