CY7C1470V25
CY7C1472V25
CY7C1474V25
Switching Characteristics
Over the Operating Range
Parameter
t
Power[18]
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
OEV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
WE, BW
x
hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
Address set-up before CLK rise
Data input set-up before CLK rise
CEN set-up before CLK rise
WE, BW
x
set-up before CLK rise
ADV/LD set-up before CLK rise
Chip select set-up
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
Data output valid after CLK rise
OE LOW to output valid
Data output hold after CLK rise
Clock to high Z
Clock to low Z
OE HIGH to output high Z
OE LOW to Output low Z
–
–
1.3
–
1.3
–
0
3.0
3.0
–
3.0
–
3.0
–
–
–
1.3
–
1.3
–
0
3.0
3.0
–
3.0
–
3.0
–
–
–
1.5
–
1.5
–
0
3.4
3.4
–
3.4
–
3.4
–
ns
ns
ns
ns
ns
ns
ns
Clock cycle time
Maximum operating frequency
Clock HIGH
Clock LOW
4.0
–
2.0
2.0
–
250
–
–
5.0
–
2.0
2.0
–
200
–
–
6.0
–
2.2
2.2
–
167
–
–
ns
MHz
ns
ns
Description
V
CC
(typical) to the first access read or write
–250
Min
1
Max
–
Min
1
–200
Max
–
Min
1
–167
Max
–
Unit
ms
Notes
16. Timing reference is 1.25 V when V
DDQ
= 2.5 V and 0.9 V when V
DDQ
= 1.8 V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a read or write operation can be
initiated.
19. t
CHZ
, t
CLZ
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 38-05290 Rev. *L
Page 22 of 31
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