CY7C1049DV33
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
JA
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two layer printed
circuit board
36-pin SOJ
Package
57.91
36.73
44-pin TSOP II
Package
Unit
50.66
17.17
C/W
C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
10 ns device
OUTPUT
50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
High Z characteristics:
3.3 V
OUTPUT
5 pF
R2
351
1.5 V
Z = 50
3.0 V
ALL INPUT PULSES
90%
10%
90%
10%
30 pF*
GND
(a)
R 317
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
(c)
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[6]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Figure 2. Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
3.0V
t
CDR
V
DR
> 2V
3.0V
t
R
Conditions
V
CC
= V
DR
= 2.0 V, CE > V
CC
– 0.3 V Industrial
V
IN
> V
CC
– 0.3 V or V
IN
< 0.3 V
Auto
Min
2.0
–
–
0
t
RC
Max
–
10
15
–
–
Unit
V
mA
mA
ns
ns
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in
(a). High Z characteristics are tested for all speeds using the test load shown
in
(c).
5. No input may exceed V
CC
+ 0.3 V.
6. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
s
or stable at V
CC(min.)
> 50
s.
Document Number: 38-05475 Rev. *G
Page 5 of 14
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