CY7C1049DV33
Switching Waveforms
Figure 3. Read Cycle No. 1
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
DATA VALID
t
PD
50%
t
HZOE
t
HZCE
HIGH
IMPEDANCE
I
CC
I
SB
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 17
t
HZOE
Notes
13. Device is continuously selected. OE, CE = V
IL
.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
16. Data IO is high impedance if OE = V
IH
.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
t
HD
DATA
IN
VALID
Document Number: 38-05475 Rev. *G
Page 7 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
