CY7C1049DV33
AC Switching Characteristics
Over the Operating Range
-10 (Industrial)
Parameter
Read Cycle
t
power[8]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power up
CE HIGH to Power down
Write Cycle Time
CE LOW to Write End
Address Set up to Write End
Address Hold from Write End
Address Set up to Write Start
WE Pulse Width
Data Set up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
100
10
–
3
–
–
0
–
3
–
0
–
10
7
7
0
0
7
5
0
3
–
–
–
10
–
10
5
–
5
–
5
–
10
–
–
–
–
–
–
–
–
–
5
100
12
–
3
–
–
0
–
3
–
0
–
12
8
8
0
0
8
6
0
3
–
–
–
12
–
12
6
–
6
–
6
–
12
–
–
–
–
–
–
–
–
–
6
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min
Max
-12 (Automotive)
Min
Max
Unit
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OL
/I
OH
and 30 pF load capacitance.
8. t
POWER
gives the minimum amount of time that the power supply must be at stable, typical V
CC
values until the first memory access is performed.
9. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (c) of
Transition is measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document Number: 38-05475 Rev. *G
Page 6 of 14
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