CY7C1049DV33
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Features
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Functional Description
The CY7C1049DV33 is a high performance CMOS Static RAM
organized as 512K words by 8-bits. Easy memory expansion is
provided by an Active LOW Chip Enable (CE), an Active LOW
Output Enable (OE), and tri-state drivers. You can write to the
device by taking Chip Enable (CE) and Write Enable (WE) inputs
LOW. Data on the eight IO pins (IO
0
through IO
7
) is then written
into the location specified on the address pins (A
0
through A
18
).
You can read from the device by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
The eight input or output pins (IO
0
through IO
7
) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CY7C1049DV33 is available in standard 400 Mil wide 36
-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Pin and function compatible with CY7C1049CV33
High speed
❐
t
AA
= 10 ns
Low active power
❐
I
CC
= 90 mA @ 10 ns (Industrial)
Low CMOS standby power
❐
I
SB2
= 10 mA
2.0 V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 36-pin (400 Mil) Molded SOJ and 44-pin
TSOP II packages
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Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
IO0
IO1
ROW DECODER
512K x 8
ARRAY
SENSE AMPS
IO2
IO3
IO4
IO5
IO6
COLUMN DECODER
POWER
DOWN
IO7
A11
A12
A13
A14
A15
A16
A17
A18
Cypress Semiconductor Corporation
Document Number: 38-05475 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 1, 2011
CYPRESS [ CYPRESS SEMICONDUCTOR ]
