CY7C1361B
CY7C1363B
CY7C1361B–Pin Definitions
Name
A
0
, A
1
, A
TQFP
(3-Chip
Enable)
37,36,32,33,
34,35,43,44,
45,46,47,48,
49,50,81,82,
99,100
TQFP
(2-Chip
Enable)
37,36,32,33,
34,35,44,45,
46,47,48,49,
50,81,82,92,
99,100
BGA
(2-Chip
Enable)
P4,N4,A2,
C2,R2,A3,
B3,C3,T3,
T4,A5,B5,
C5,T5,A6,
B6,C6,R6
fBGA
(3-Chip
Enable)
I/O
Description
Input-
Address Inputs used to select one of the
R6,P6,A2,
A10,B2,B10, Synchronous
256K address locations.
Sampled at the
rising edge of the CLK if ADSP or ADSC is
P3,P4,P8,
P9,P10,P11,
active LOW, and CE
1
, CE
2
, and CE
3[2]
are
R3,R4,R8,
sampled active. A
[1:0]
feed the 2-bit counter.
R9,R10,R11
B5,A5,A4,
B4
B7
Input-
Byte Write Select Inputs, active LOW.
Qual-
Synchronous ified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
Synchronous When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on
BW
[A:D]
and BWE).
Input-
Clock
Clock Input.
Used to capture all
synchronous inputs to the device. Also used
to increment the burst counter when ADV is
asserted LOW, during a burst operation.
BW
A,
BW
B
BW
C,
BW
D
GW
93,94,95,96 93,94,95,96 L5,G5,G3,
L3
88
88
H4
CLK
89
89
K4
B6
CE
1
98
98
E4
A3
CE
2
97
97
B2
B3
Input-
Chip Enable 1 Input, active LOW.
Sampled
Synchronous on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3[2]
to
select/deselect the device. ADSP is ignored
if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH.
Synchronous Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3[2]
to
select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled
Synchronous on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/
deselect the device.
Input-
Output Enable, asynchronous input,
Asynchronous
active LOW.
Controls the direction of the I/O
pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
OE is masked during the first clock of a read
cycle when emerging from a deselected state.
Input-
Advance Input signal, sampled on the
Synchronous
rising edge of CLK.
When asserted, it
automatically increments the address in a
burst cycle.
Input-
Address Strobe from Processor, sampled
Synchronous
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
CE
3[2]
92
–
–
A6
OE
86
86
F4
B8
ADV
83
83
G4
A9
ADSP
84
84
A4
B9
Document #: 38-05302 Rev. *B
Page 7 of 34
CYPRESS [ CYPRESS SEMICONDUCTOR ]
