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CY7C1361B-133BGC 参数 Datasheet PDF下载

CY7C1361B-133BGC图片预览
型号: CY7C1361B-133BGC
PDF下载: 下载PDF文件 查看货源
内容描述: 9兆位( 256K ×36 / 512K ×18 )流通型SRAM [9-Mbit (256K x 36/512K x 18) Flow-Through SRAM]
分类和应用: 静态存储器
文件页数/大小: 34 页 / 820 K
品牌: CYPRESS [ CYPRESS ]
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CY7C1361B  
CY7C1363B  
CY7C1363B: Pin Definitions (continued)  
TQFP  
(3-Chip  
Enable)  
TQFP  
(2-Chip  
Enable)  
BGA  
fBGA  
(3-Chip  
Enable)  
(2-Chip  
Enable)  
Name  
VSS  
I/O  
Description  
Ground for the core of the device.  
17,40,67,90 17,40,67,90 D3,D5,E3, C4,C5,C6,  
E5,F3,F5, C7,C8,D5,  
Ground  
G5,H3,  
D6,D7,E5,  
H5,K3,K5, E6,E7,F5,  
L3,M3,  
M5,N3,  
F6,F7,G5,  
G6,G7,H1,  
N5,P3,P5 H2,H5,H6,  
H7,J5,J6,J7,  
K5,K6,K7,L5  
,L6,L7,M5,  
M6,M7,N4,  
N8  
VSSQ  
TDO  
5,10,21,26, 5,10,21,26,  
55,60,71,76, 55,60,71,76,  
I/O Ground  
Ground for the I/O circuitry.  
U5  
P7  
JTAG serial Serial data-out to the JTAG circuit.  
output  
Delivers data on the negative edge of TCK.  
Synchronous If the JTAG feature is not being utilized, this  
pin should be left unconnected. This pin is  
not available on TQFP packages.  
TDI  
U3  
P5  
JTAG serial Serial data-In to the JTAG circuit.  
input  
Sampled on the rising edge of TCK. If the  
Synchronous JTAG feature is not being utilized, this pin  
can be left floating or connected to VDD  
through a pull up resistor. This pin is not  
available on TQFP packages.  
TMS  
U2  
U4  
R5  
R7  
JTAG serial Serial data-In to the JTAG circuit.  
input  
Sampled on the rising edge of TCK. If the  
Synchronous JTAG feature is not being utilized, this pin  
can be disconnected or connected to VDD  
.
This pin is not available on TQFP packages.  
TCK  
NC  
JTAG-  
Clock  
Clock input to the JTAG circuitry. If the  
JTAG feature is not being utilized, this pin  
must be connected to VSS. This pin is not  
available on TQFP packages.  
1,2,3,6,7,16, 1,2,3,6,7,16, B1,B7,C1, A1,A5,B1,  
25,28,29,30, 25,28,29,30, C7,D2,D4, B4,B11,C1,  
38,39,42,51, 38,39,42,43, D7,E1,E6, C2,C10,D1,  
52,53,56,57, 51,52,53,56, H2,F2,G1, D10,E1,E10,  
66,75,78,79, 57,66,75,78, G6,H7,J3, F1,F10,G1,  
No Connects. Not internally connected to  
the die. 18M, 36M, 72M, 144M and 288M  
are address expansion pins are not inter-  
nally connected to the die.  
95,96  
79,95,96 J5,K1,K6, G10,H3,H9,  
L4,L2,L7, H10,J2,J11,  
M6,N2,N7 K2,K11,L2,  
,L7,P1,P6, L11,M2,M11,  
R1,R5,R7, N2,N5,N6,  
T1,T4,U6 N7,N10,N11,  
P1,P2,R2  
VSS/DNU  
14  
14  
Ground/DNU This pin can be connected to Ground or  
should be left floating.  
Document #: 38-05302 Rev. *B  
Page 12 of 34  
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